Semiconductor integrated circuit device and its...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S612000, C438S613000, C438S622000, C257S758000, C257S759000

Reexamination Certificate

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06867123

ABSTRACT:
A semiconductor wafer which has finished formation of a relocating wiring layer thereon is stored and after determination of a design, solder bumps are formed over bump lands (one end of the relocating wiring layer) in accordance with a pattern which differs with a design, whereby a function or characteristic depending on the design is selected. The semiconductor wafer is then cut into a plurality of semiconductor chips, whereby a wafer level CSP is available.

REFERENCES:
patent: 20020046880 (2002-04-01), Takubo et al.
patent: 20040007778 (2004-01-01), Shinozaki et al.
patent: 7-161761 (1995-06-01), None
patent: 7-263451 (1995-10-01), None
patent: 10-189813 (1998-07-01), None
patent: 11-40563 (1999-02-01), None
patent: 2000-216253 (2000-08-01), None
patent: WO9923696 (1999-05-01), None

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