Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-10-29
2004-02-10
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S272000, C438S276000, C438S291000
Reexamination Certificate
active
06689662
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices, and more particularly to power MOSFET devices.
BACKGROUND OF THE INVENTION
Power MOSFET devices are employed in applications such as automobile electrical systems, power supplies, and power management applications. Such devices should sustain high voltage in the off-state and yield low voltage and high saturation current density in the on-state.
FIG. 1
illustrates a typical structure for an N-channel power MOSFET. An N-epitaxial silicon layer
1
formed over an N+ silicon substrate
2
contains p-body regions
5
a
and
6
a
, and N+ source regions
7
and
8
for two MOSFET cells in the device. P-body regions
5
and
6
may also include deep p-body regions
5
b
and
6
b
. A source-body electrode
12
extends across certain surface portions of epitaxial layer
1
to contact the source and body regions. The N-type drain for both cells is formed by the portion of N-epitaxial layer
1
extending to the upper semiconductor surface in
FIG. 1. A
drain electrode (not separately shown) is provided at the bottom of N+ substrate
2
. An insulated gate electrode
18
comprising oxide and polysilicon layers lies over the channel and drain portions of the body.
The on-resistance of the conventional MOSFET shown in
FIG. 1
is determined largely by the drift zone resistance in epitaxial layer
1
. The drift zone resistance is in turn determined by the doping and the layer thickness of epitaxial layer
1
. However, to increase the breakdown voltage of the device, the doping concentration of epitaxial layer
1
must be reduced while the layer thickness is increased. Curve
20
in
FIG. 2
shows the on-resistance per unit area as a function of the breakdown voltage for a conventional MOSFET. Unfortunately, as curve
20
shows, the on-resistance of the device increases rapidly as its breakdown voltage increases. This rapid increase in resistance presents a problem when the MOSFET is to be operated at higher voltages, particularly at voltages greater than a few hundred volts.
FIG. 3
shows a MOSFET that is designed to operate at higher voltages with a reduced on-resistance. This MOSFET is disclosed in paper No. 26.2 in the Proceedings of the IEDM, 1998, p. 683. This MOSFET is similar to the conventional MOSFET shown in
FIG. 2
except that it includes p-type doped regions
40
and
42
which extend from beneath the body regions
5
and
6
into to the drift region of the device. The p-type doped regions
40
and
42
cause the reverse voltage to be built up not only in the vertical direction, as in a conventional MOSFET, but in the horizontal direction as well. As a result, this device can achieve the same reverse voltage as in the conventional device with a reduced layer thickness of epitaxial layer
1
and with increased doping concentration in the drift zone. Curve
25
in
FIG. 2
shows the on-resistance per unit area as a function of the breakdown voltage of the MOSFET shown in FIG.
3
. Clearly, at higher operating voltages, the on-resistance of this device is substantially reduced relative to the device shown in
FIG. 1
, essentially increasing linearly with the breakdown voltage.
The structure shown in
FIG. 3
can be fabricated with a process sequence that includes multiple epitaxial deposition steps, each followed by the introduction of the appropriate dopant. Unfortunately, epitaxial deposition steps are expensive to perform and thus this structure is expensive to manufacture.
Accordingly, it would be desirable to provide a method of fabricating the MOSFET structure shown in
FIG. 3
that requires a minimum number of deposition steps so that it can be produced less expensively.
SUMMARY OF THE INVENTION
In accordance with the present invention, a power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches, thus forming the p-type doped regions that cause the reverse voltage to be built up in the horizontal direction as well as the vertical direction.
In accordance with one aspect of the invention, the material filling the trench is polysilicon.
In accordance with yet another aspect of the invention, the polysilicon filling the trench is at least partially oxidized. Alternatively the polysilicon may be subsequently recrystallized to form single crystal silicon.
In accordance with another aspect of the invention, the material filling the trench is a dielectric such as silicon dioxide, for example.
In accordance with another aspect of the invention, the material filling the trench may include both polysilicon and a dielectric.
In accordance with another aspect of the invention, a method is provided for forming a power MOSFET. The method begins by providing a substrate of a first conductivity type and depositing an epitaxial layer on the substrate. The epitaxial layer has a first conductivity type. First and second body regions are formed in the epitaxial layer to define a drift region therebetween. The body regions have a second conductivity type. First and second source regions of the first conductivity type are formed in the first and second body regions, respectively. A plurality of trenches are formed in the drift region of the epitaxial layer. The trenches are filled with a material having a dopant of the second conductivity type. The trenches extend toward the substrate from the first and second body regions. At least a portion of the dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.
REFERENCES:
patent: 4959699 (1990-09-01), Lidow et al.
patent: 5216275 (1993-06-01), Chen
patent: 5326711 (1994-07-01), Malhi
patent: 5404040 (1995-04-01), Hshieh et al.
patent: 5744719 (1998-04-01), Werner
patent: 5895951 (1999-04-01), So et al.
patent: 5973360 (1999-10-01), Tihanyi
patent: 6184555 (2001-02-01), Tihanyi et al.
patent: 6452230 (2002-09-01), Boden, Jr.
patent: 2002/0094635 (2002-07-01), Hirler et al.
patent: 197 48 523 (1999-05-01), None
patent: 198 00 647 (1999-05-01), None
patent: 0053854 (1985-05-01), None
patent: 0 053 854 (1986-05-01), None
patent: 0 973 203 (1999-03-01), None
patent: 2314206 (1997-12-01), None
patent: 08264772 (1996-10-01), None
patent: WO 99/23703 (1999-03-01), None
G. Deboy et al., “A New Generation of High Voltage MOSFETS Breaks the Limit Line of Silicon,” Electron Devices Meeting, San Francisco, CA, Dec. 6-9, 1998, Paper No. 26.2.1, pp. 683-685, Sponsored by Electron Devices Society of IEEE.
X. Chen, Theory of a Novel Voltage Sustaining (CB) Layer for Power Devices, Chinese Journal of Electronics, vol. 7, No. 3, Jul. 1998.
T. Fujihira et al., “Simulated Superior Performance of Semiconductor Superjunction Devices,” Proceedings of 1998 International Symposium on Power Semiconductor Devices & ICs, Kyoto, pp. 423-426.
T. Fujihira, “Theory of Semiconductor Superjunction Devices,” Jpn. J. Appl. Phys., vol. 36 (1997), pp. 6254-6262.
Jean-Marie Peter, “Power Semiconductors: New Devices Pursue Lower On-Resistance, Higher Voltage Operation,” PCIM, Jan. 1999, pp. 26-32.
“Power Semiconductors Proliferate: Expanding Product Lines and Advancing Process Technology Promise Higher Performance in Varied Applications,” Electronic Products, Jul. 1999, pp. 23-24.
L. Lorenz et al., “Improved MOSFET: An Important Milestone Toward a New Power Mosfet Generation,” PCIM, Sep. 1998, pp.
General Semiconductor Inc.
Huynh Yennhu B.
Jr. Carl Whitehead
Mayer Fortkort & Williams PC
Mayer, Esq. Stuart H.
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