Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-11
2004-02-24
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C438S656000, C438S241000
Reexamination Certificate
active
06696337
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and a method of manufacturing the same. More particularly, this invention relates to a technology which will be useful when applied to a semiconductor integrated circuit device in which bit line conductors disposed in a memory cell region of a DRAM (Dynamic Random Access Memory) and first level interconnect conductors disposed in a peripheral circuit region of the DRAM are formed by the same layer.
Recent large capacity DRAMs employ a stacked capacitor structure in which an information storage capacitor device is disposed over a memory cell selection MISFET so as to supplement a decrease of a stored charge quantity (Cs) of the information storage capacitor device due to scaling-down of memory cells.
The information storage capacitor device of the stacked capacitor structure is formed by serially laminating a storage electrode (lower electrode), a capacity insulating film and a plate electrode (upper electrode). The storage electrode of the information storage capacitor device is connected to one of the semiconductor regions (source region and drain region) of an n-channel memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor). The plate electrode is constituted as an electrode common to a plurality of memory cells and a predetermined fixed potential (plate potential) is supplied to this plate electrode.
A bit line for writing and reading data is connected to the other of the semiconductor regions of the memory cell selection MISFET. A bit line conductor is disposed between the memory cell selection MISFET and the information storage capacitor device or over the information storage capacitor device. The structure wherein the information storage capacitor device is disposed over the bit line conductor is referred to as a “capacitor over bit line (COB)” structure.
A DRAM having the COB structure is described, for example, in U.S. Pat. No. 5,604,365 issued on Feb. 18, 1977 (corresponding to JP-A-7-122654 laid open on).
In the DRAM described in the above-mentioned reference, bit lines constituted by a polysilicon film (or a policide film) are disposed over a memory cell selection MISFET the gate electrode (word line) of which is constituted by a polysilicon film or a laminate film (policide film) of the polysilicon film and a tungsten silicide (WSix) film, and an information storage capacitor device comprising a storage electrode formed by a polysilicon film, a capacity insulating film formed by a laminate film of a silicon oxide film and a silicon nitride film and a plate electrode formed by a poly-silicon film is disposed over the bit lines.
A higher integration density has been required for the DRAM having such a COB structure, too. A multi-level interconnect structure has become indispensable with the progress of scaling-down of interconnect conductors, and a three-layered interconnect structure having a minimum line width of 0.3 &mgr;m has been employed in 64 Mbit DRAMs, for example.
The adoption of a multi-level interconnect technology for arranging the interconnect conductors in a multi-level configuration invites an increase in the number of process steps in the conductor formation process and eventually causes a drop of through-put of a production process. Therefore, the increase of the number of interconnect conductor levels must be reduced essentially to minimum. A proposal has been made as one of the methods of solving the problem which forms interconnect conductors of a peripheral circuit in the same process when bit lines for transferring directly memory cell information to a sense amplifier of the peripheral circuit portion are formed. In other words, a technology has been proposed which forms a part of the interconnect conductors (more specifically, a first level interconnect conductor) among the interconnect conductors of the peripheral circuit portion at the same level by the same process step as the formation step of the bit lines.
This technology is described, for example in U.S. Pat. No. 5,604,365 described above and in IEDM '94, p.635.
SUMMARY OF THE INVENTION
Nonetheless, the inventors of the present invention have found out the following problems in the technology described above in which the bit line conductor of the memory cell portion and the first level interconnect conductor are formed by the same step.
In other words, it is required for the bit line to reduce its parasitic capacity in order to improve detection accuracy of charges stored in an information storage capacitor device, and it is required for an interconnect conductor of a peripheral circuit portion to secure a sufficiently low resistance in order to prevent the drop of an operation speed of the peripheral circuit portion.
To satisfy both of these requirements, the thickness of the bit line as well as the thickness of a conductor film constituting the interconnect conductor of the peripheral circuit portion must be optimized, respectively. When tungsten is employed, for example, it is necessary to set the thickness of the bit line conductor to 0.1 &mgr;m and the thickness of the interconnect conductor of the peripheral circuit portion to 0.3 &mgr;m. Therefore, it is necessary that after a thin conductor film is formed and processed on a semiconductor substrate so as to form the bit line conductor at the memory cell portion, a thick conductor film must be formed and processed on the semiconductor substrate to form the interconnect conductor in the peripheral circuit portion. As a result, not only the number of process steps but also the production time increase remarkably.
It is an object of the present invention to provide a technology which can reduce a parasitic capacity of bit lines and can also reduce a resistance of interconnect conductors of a peripheral circuit portion in a semiconductor integrated circuit device of the type in which bit lines and first level interconnect conductors are formed at the same level.
It is another object of the present invention to provide a technology which can suppress an increase of the number of process steps and can form bit line conductors having a low parasitic capacity and interconnect conductors of a peripheral circuit portion having a low resistance without increasing the production time.
The above and other objects and novel features of the present invention will become more apparent from the following description of the specification when taken in conjunction with the accompanying drawings.
According to one aspect of the present invention, there is provided a semiconductor integrated circuit device including a DRAM having a memory cell portion, a peripheral circuit portion and bit line conductors for exchanging information between the memory cell portion and the peripheral circuit portion, wherein each interconnect conductor of the peripheral circuit portion comprises a single or a plurality of conductor films, at least one layer of the conductor films is made of the same material as that of the conductor film constituting a bit line conductor and is formed at the same level as the conductor film of the bit line conductors (that is, it is formed by the same step as that of the conductor film), and the film thickness of the interconnect conductors in the peripheral circuit portion is greater than that of the bit line conductors.
In the semiconductor integrated circuit device described above, each interconnect conductor in the peripheral circuit portion (hereinafter called merely the “interconnect conductor”) and each bit line conductor is formed by the same step. In consequence, the number of process steps does not increase and through-put does not drop, either. Because the film thickness of the interconnect conductor is greater than that of the bit line conductor, the resistance of the interconnect conductor can be reduced and at the same time, the parasitic capacity of the bit line conductor can be reduced by reducing the film thickness of the bit line conductor. As a result, a response speed of the peripheral cir
Asano Isamu
Tsu Robert
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Huynh Yennhu B
Jr. Carl Whitehead
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