Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

1999-04-01

2004-06-01

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S729000

Reexamination Certificate

active

06745355

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, for instance a digital signal processor (referred to as “DSP” hereinafter), a microprocessor and so forth, more particularly, the invention relates to a semiconductor integrated circuit which can be used for the purpose of logical verification of the internal parts of the circuit and the data verification of the internal register.
Generally, the semiconductor integrated circuit includes a plurality of processing circuits for executing necessary processes. The term ‘processing circuit’ herein refers to a combination circuit which is constructed with logical circuits, for instance as an AND circuit, an OR circuit and so forth. The logic level of the output signal from such combination circuit is determined to be a predetermined logical level corresponding to the logical level of the input signal supplied thereto. However, should such combination circuit have a certain defect and/or should the change with the passage of time relating to its performance be not in an allowable range, the output signal comes to have a logical level which is neither the desired logical level nor responds to the logical level of the input signal. Thus, it is necessary to verify whether the semiconductor integrated circuit including such combination circuit normally operates or not, and execution of the logical verification increases its importance.
For the purpose of carrying out this logical verification, the semiconductor integrated circuit includes a plurality of scan-path registers. Each scan-path register is constituted with a data maintaining circuit which receives the input signal to the combination circuit or the output circuit therefrom. In case of ordinarily processing the signal which is externally inputted to the semiconductor integrated circuit (referred to as “ordinary processing” hereinafter), the scan-path register operates to transfer its received input signal to the combination circuit or to output the signal outputted by the combination circuit to a certain circuit in the next stage. This circuit in the next stage indicates such a circuit that receives the output signal from the combination circuit and applies a desired processing thereto. In time of executing the logical verification over the combination circuit (referred to as “logical verification time” hereinafter), the scan-path registers are connected in sequence with each other, thereby constituting a shift register as a whole.
Regarding to the logical verification of the semiconductor integrate circuit using the scan-path registers, there has been published by Oki Denki Kogyo K.K. an article entitled “Scan-path Register.” In the following, an example of a data system connection relating to the logical verification operation will be explained by way of the semiconductor integrated circuit using the scan-path register as disclosed in the above article, referring to
FIG. 10
of the accompanying drawings.
Referring to
FIG. 10
, there is shown a diagram of a conventional semiconductor integrated circuit
800
which includes three combination circuits
811
-
1
through
811
-
3
to be logically verified. The semiconductor integrated circuit
800
also includes a plurality of signal terminals for exchanging the signal with external portions, to be more concrete, an input terminal MD for a mode setting signal, a first clock input terminal CL
1
, a second clock input terminal CL
2
, a data input terminal
880
for the Scan-path, and a data output terminal
881
for the Scan-path.
The input terminal MD for the mode setting signal receives the mode setting signal which is used for switching the operation of the scan-path register from the serial operation to the parallel operation or vice versa, both operations being described later. The first clock input terminal CL
1
receives the first clock signal which is used under the first operating condition, that is, under the ordinary operating condition. The second clock input terminal CL
2
receives the second clock signal under the second operating condition, namely in the logical verification time. The data input terminal
880
for the scan-path receives a data signal SIN which is used for the logical verification in the logical verification time. The data output terminal
881
for the scan-path outputs the data signal SOUT which is obtained as a result of the logical verification.
The semiconductor integrated circuit
800
further includes scan-path registers
810
-
1
through
810
-n and
820
-
1
through
820
-n (n: positive integer) as the data maintaining circuit, and a control signal generating circuit
840
.
The scan-path registers
810
-K (or
820
-K) (K: positive integer but 1≦K≦n) include a clock input terminal CK, a first data input terminal D, a second data input terminal SI, a first control signal input terminal K
1
, a second control signal input terminal K
2
, and an output terminal Q.
The control signal generating circuit
840
is connected with the mode setting signal input terminal MD, the first clock input terminal CL
1
, and the second clock input terminal CL
2
, respectively. This control signal generating circuit
840
generates a plurality of control signals C/!C, PC/!PC, and SC/!SC. The control signal C/!C represents either one or both of a control signal C and an inverted control signal !C having a logical level complementary to that of the control signal C.
The control signal C/!C is inputted to the clock input terminal CK of the scan-path register
810
-K (or
820
-K). The control signal PC/!PC is inputted to the first control signal input terminal K
1
of the scan-path register
810
-K (or
820
-K). The control signal SC/!SC is inputted to the second control signal input terminal K
2
of the scan-path register
810
-K (or
820
-K).
The output signal from the combination circuit
811
-
1
is inputted to the first data input terminal D of the scan-path register
810
-K. The output signal from the combination circuit
811
-
2
is inputted to the first data input terminal D of the scan-path register
820
-K. The second data input terminal SI of the scan-path register
810
-K is connected with the output terminal Q of the scan-path register
810
-(K−1). However, in case of K=1, the second data input terminal SI is connected to the data input terminal
880
for the scan-path.
The second data input terminal SI of the scan-path register
820
-K is connected with the output terminal Q of the scan-path register
820
-(K−1). However, in case of K=1, the second data input terminal SI is connected with the output terminal Q of the scan-path register
810
-n. The output terminal Q of the scan-path register
810
-K is also connected with the combination circuit
811
-
2
while the output terminal Q of the scan-path register
820
-K is also connected with the combination circuit
811
-
3
. In case of K=n, however, the output terminal Q is also connected with the output terminal
881
for the Scan-path.
It will now be explained in the following how to carry out the logical verification against the combination circuit by means of the scan-path register.
(1) Test Serial Input Operation
In this operation, the data SIN (referred to as “test vector” hereinafter) for logical verification is serially inputted to the data input terminal
880
for the Scan-path, thereby storing the data in all the scan-path registers
810
-
1
through
810
-n and
820
-
1
through
820
-n with the help of the shift operation. This operation is carried out in response the second clock signal CL
2
.
(2) Test Parallel Operation
In this operation, the test vector SIN stored in the scan-path registers, which are disposed on the input side of the combination circuit to be logically verified, is inputted to the above combination circuit, of which the output is then given to and stored in the scan-path registers which are disposed on the output side of the above combination circuit. This operation is performed in response to the secon

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