Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-03-04
2004-08-10
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S332000, C257S335000, C257S339000, C257S400000, C257S401000, C257S409000, C257S500000, C257S501000, C257S502000, C257S510000
Reexamination Certificate
active
06773995
ABSTRACT:
CROSS-REFERENCE TO RELATED CASES
This application claims the priority of Korean Patent Application No. 2002-0043697, filed Jul. 24, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power device and a method for manufacturing the same.
2. Description of the Related Art
Double-diffused metal oxide semiconductor (DMOS) transistors, which are MOS-type transistors driven by voltage and which may bear high current, have begun attracting greater attention. DMOS transistors integrated with bipolar-type integrated circuits may be classified as lateral DMOS (LDMOS) transistors, or vertical DMOS (VDMOS) transistors, depending on the direction of current flowing therein. In particular, for DMOS transistors operating at a high voltage, it is advantageous that the DMOS transistors be VDMOS transistors because VDMOS transistors occupy smaller area on a substrate than LDMOS transistors. Among VDMOS transistors, N-channel VDMOS transistors, which have sound electrical characteristics, are typically used in bipolar-type integrated circuits.
N-channel VDMOS transistors are connected to N+ buried layers, using the N+ buried layers as drains. The drains may be heavily doped with impurity ions, thus isolation layers with considerable surface areas are required in order to isolate VDMOS transistors from each other. In a case where doping concentration is increased and drive-in time (e.g., time necessary to drive dopant atoms deeper into a semiconductor wafer of the device) long, a large-sized semiconductor device with a wider isolation layer may be required in order to reduce a drain-source on-resistance (Rdson), so as to maintain breakdown voltage of the semiconductor device. Where high-dose ion implantation is used for reducing Rdson, a thermal process requiring a sufficient amount of heat may be needed to diffuse impurity ions into a lower portion of the semiconductor device.
Due to the increased heat required, the area of the semiconductor device may increase in a horizontal direction during the diffusion. Additionally where high-energy ion implantation is used to reduce Rdson, since high-dose doping may be difficult, high-energy ion implantation techniques may be limited when reducing Rdson, since these techniques cannot avoid the diffusion of impurity ions in a vertical direction. Thus, high-energy ion implantation techniques may be disadvantageous to the scaling of the semiconductor device. As a result, a trade-off may exist between a desire to reduce Rdson, and a desire to reduce an area of an isolation layer.
However, the need for mounting small-sized, highly-integrated semiconductor devices that consume a small amount of power on a semiconductor chip continues to increase. Thus, a technique for achieving appropriate performance from semiconductor devices by reducing Rdson and scaling down the semiconductor devices along horizontal and vertical dimensions is desired.
SUMMARY OF THE INVENTION
Exemplary embodiments of the present invention provide a method for manufacturing a semiconductor device, such as a DMOS transistor, for example, by which Rdson and the size of a semiconductor chip containing the device may be reduced. Exemplary embodiments of the present invention also may provide a DMOS transistor which has a small Rdson, which may be advantageous in the integration of a semiconductor device.
In an exemplary embodiment, the present invention is directed to a method of forming a semiconductor device, where a first layer may be formed on a semiconductor substrate, and one or more isolation trenches may be formed and filled with an isolation layer. A second layer may be formed on the first layer and semiconductor substrate, and a plurality of drain trenches may be formed therein. A pair of plug-type drains may be formed in the trenches, to be separated from the isolation layer by a dielectric spacer. Gates and source areas may be formed on a resultant structure containing the plug-type drains. Accordingly, current may be increased with a reduction in drain-source on resistance, and an area of the isolation layer can be efficiently reduced, as compared to an existing isolation layer, potentially resulting in a reduction in chip area.
According to a further exemplary embodiment, the present invention is directed to a method of manufacturing a double-diffused metal oxide semiconductor (DMOS) transistor. A buried layer containing impurity ions of a second conductivity type may be formed in a semiconductor substrate containing impurity ions of a first conductivity type. Isolation trenches may be formed in the buried layer and semiconductor substrate, and an isolation layer may be formed in the isolation trenches. An epitaxial layer containing impurity ions of the second conductivity type may be grown on the buried layer and isolation layer, and drain trenches may be formed in isolation layer. A dielectric spacer may be formed on sidewalls of the drain trenches, and plug-type drains containing impurity ions of the second conductivity type may be formed on the dielectric spacer within the drain trenches. Gates and source areas may be formed on a resultant structure containing the plug-type drains.
According to another exemplary embodiment, the present invention is directed to a double-diffused metal oxide semiconductor transistor that may include a semiconductor substrate, a buried layer, an isolation layer, an epitaxial layer, plug-type drains, a dielectric spacer, body areas, source areas, and gate oxide layers and gates. The semiconductor substrate may include impurity ions of a first conductivity type. The buried layer may be formed on the semiconductor substrate and include impurity ions of a second conductivity type, different from the first conductivity type. The isolation layer may be formed in the buried layer and semiconductor substrate. The epitaxial layer may be formed on the isolation layer and buried layer and may include impurity ions of the second conductivity type. The plug-type drains may be formed in the epitaxial layer and may include impurity ions of the second conductivity type. The dielectric spacer may be formed on outer sidewalls of the plug-type drains adjacent to the isolation layer. The body areas may be formed in the epitaxial layer and include impurity ions of the first conductivity type. The source areas may be formed in the body areas and include impurity ions of the second conductivity type, and the gate oxide layers and gates may be formed on the source areas.
REFERENCES:
patent: 5682048 (1997-10-01), Shinohara et al.
patent: 6194761 (2001-02-01), Chiozzi et al.
Lee Soo-Cheol
Shin Hwa-Sook
Harness Dickey
Louie Wai-Sing
Pham Long
Samsung Electronics Co,. Ltd.
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