Methods of forming floating-gate FFRAM devices

Details Methods of forming floating-gate FFRAM devices Methods of forming floating-gate FFRAM devices

1997-11-19

1999-08-17

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438266, 438241, 438152, 438 3, H01L 21336

Patent

active

059407050

ABSTRACT:
Methods of forming floating-gate ferroelectric random-access-memory (FFRAM) devices include the steps of forming vertically integrated FFRAM unit cells having floating-gate transistors and access transistors positioned at different levels on a semiconductor substrate to increase the density at which the unit cells may be integrated. Preferred methods include the steps of forming a first transistor having opposing floating and control gate electrodes, at a surface of a semiconductor substrate, and then forming a first insulating layer having a first contact hole therein, on the first transistor. The first transistor comprises a layer of ferroelectric material between the floating and control gate electrodes, which can be polarized in respective first and second states to retain logic 1 and logic 0 data. Steps are then performed to form a first electrical interconnect (e.g., conductive plug) in the first contact hole and electrically coupled to the control gate electrode. Then, a series of steps are performed to form a vertically integrated second transistor on the first insulating layer. Here, the second transistor is formed as a field effect transistor having a drain region electrically coupled to the control gate of the first transistor by the first electrical interconnect. The steps of forming a second transistor may include the steps of forming a silicon-on-insulator (SOI) substrate on the first insulating layer, forming a gate electrode on the silicon portion of the SOI substrate, and then forming source, drain and channel regions in the silicon portion of the SOI substrate.

REFERENCES:
patent: 5345414 (1994-09-01), Nakamura
patent: 5675530 (1997-10-01), Hirano et al.
patent: 5675536 (1997-10-01), Sim
patent: 5675537 (1997-10-01), Bill et al.
patent: 5770483 (1998-06-01), Kadosh et al.
patent: 5834341 (1998-11-01), Chen

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