Method of making a hybrid SOI device that suppresses...

Details Method of making a hybrid SOI device that suppresses... Method of making a hybrid SOI device that suppresses...

2000-12-07

2004-04-27

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S304000, C438S305000

Reexamination Certificate

active

06727149

ABSTRACT:

FIELD OF INVENTION
The present invention relates to Silicon-on-Insulator devices and, more particularly, to a method of making Silicon-on-Insulator devices having suppressed floating body effects.
BACKGROUND OF THE INVENTION
Integrated Circuits (IC) containing Silicon On Insulator (SOI) devices are becoming increasingly important due to their speed. An SOI device (i.e., a transistor) is typically formed in a layer of semiconductor material overlaying an insulating layer formed in a semiconductor substrate.
A prior art SOI transistor such as that shown in
FIG. 1
includes a source region
14
and a drain region
14
which are separated from each other by a channel region
12
. A gate
15
is separated from the device by a gate oxide layer
13
. Both the source and drain regions are of the same conductivity type opposite to that of the body region
16
. For example, when the body region is of a p-type material, the source and drain regions are of n-type materials. The source and drain regions typically have a higher dopant concentration than the body region.
There are two known types of SOI transistors, namely partially depleted SOI transistors and fully depleted SOI transistors.
In a partially depleted SOI transistor, such as the known SOI transistor
10
of
FIG. 1
, when channel
12
is formed between source/drain regions
14
, depletion region
16
extends only partially into body layer
18
. Unlike a conventional MOS transistor, a typical SOI transistor, such as SOI transistor
10
, does not have a body contact. In other words, body layer
18
of SOI
10
floats. Consequently, when a DC current flows between the source and drain regions
14
, holes generated due to impact ionization, thermal effects or gate-induced drain leakage, flow to the floating body layer
18
thereby affecting its potential and causing its threshold voltage to change (i.e., due to the transistor body effect). Similarly, when the gate or source/drain voltage is modulated (i.e. during transient events), the potential at body layer
18
is changed, which modulates the SOI threshold voltage.
In a fully depleted SOI, such as the known SOI
20
of
FIG. 2
, the width of body layer
22
overlaying insulating layer
24
is smaller than the width of the depletion region that extends into body layer
18
when channel
12
is formed. Therefore, the potential at body layer
18
remains fixed. Accordingly, the threshold voltage of SOI transistor
20
remains unchanged and is not subject to the body effect.
Although SOI
20
does not suffer from threshold voltage variations due to body effect, it is difficult to controllably manufacture a thin body layer
22
that fully depletes when channel
12
is formed.
Therefore, a need continues to exists for an SOI device which has a suppressed body-effect and which can be controllably manufactured.
SUMMARY OF THE INVENTION
A method of making a Silicon-on-Insulator (SOI) transistor, in accordance with one embodiment of the present invention, comprises forming a body layer that fully depletes when the SOI transistor is in a conductive state; and forming first p
+
regions adjacent each of the SOI transistor source/drain regions to thereby adjust the threshold voltage.
In some embodiments, an additional implant step is carried out to form second p
+
regions adjacent the first implant regions to suppress the punch-through current.


REFERENCES:
patent: 5593907 (1997-01-01), Anjum et al.
patent: 5650340 (1997-07-01), Burr et al.
patent: 5716861 (1998-02-01), Moslehi
patent: 5753958 (1998-05-01), Burr et al.
patent: 5757045 (1998-05-01), Tsai et al.
patent: 5786620 (1998-07-01), Richards et al.
patent: 5825066 (1998-10-01), Buynoski
patent: 5856225 (1999-01-01), Lee et al.
patent: 6093610 (2000-07-01), Rodder
patent: 6107129 (2000-08-01), Gardner et al.
patent: 6124616 (2000-09-01), Dennison et al.
patent: 6268640 (2001-07-01), Park et al.
patent: 6271095 (2001-08-01), Yu
patent: 6271132 (2001-08-01), Xiang et al.
patent: 6291278 (2001-09-01), Xiang et al.

Affiliated with

Also associated with

Rating

Method of making a hybrid SOI device that suppresses... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making a hybrid SOI device that suppresses..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a hybrid SOI device that suppresses... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3247683