Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2003-05-30
2004-07-06
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C324S527000
Reexamination Certificate
active
06760875
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to integrated circuit devices and, more specifically, to a circuit and method for controlling the ability of such devices to enter into a test mode.
BACKGROUND OF THE INVENTION
The testing of memory devices in the prior art generally involves receiving inputs from several memory addresses at one time into a test vector decoding circuit and performing logic functions on those inputs. The resulting output test vectors are used to perform operations on various devices, such as compressing address circuits or disabling regulators. Once testing has been completed, the values of the output test vectors will remain consistent for the purpose of driving circuits during non-test operations of the memory device.
One possible method of triggering the test mode as disclosed in the prior art is to use two signals. For example, a WCBR signal (Write enable signal at low with the CAS signal transmitted Before the RAS signal) sent during the transmission of a supervoltage signal is often used. The supervoltage signal will have a higher potential than the standard supply voltage. This supervoltage signal may generally be applied consistently throughout both test and non-test modes of the memory device. Only during the test mode, however, will the WCBR signal deliberately appear.
Nevertheless, it is possible that placing the memory device in a noisy environment may result in an errant WCBR signal being sent to the test vector decode circuit during a non-test mode. For example, memory devices are often subjected to a burn-in process, wherein the memory devices are operated at higher-than-usual voltages and temperatures in order to identify weak memory devices. This noisy process could result in random signals being transmitted through the write enable, CAS, and RAS paths so as to trigger a false WCBR signal and latch the test vector decode circuit. In that event, the test vector decode circuit would process the memory address inputs at their present random state. The resulting output vectors might not have the proper values. As a consequence, parts of the integrated device that should receive a particular value may no longer do so. For example, it is possible that one of the output vectors may represent an errant “ground V
BB
” signal transmitted at the wrong time. That would ground the substrate of the memory device, thereby causing a high current mode and eventual meltdown of the circuitry. Therefore, it would be a benefit to the art to be able to prevent the memory circuit from inadvertently entering a test mode.
SUMMARY OF THE INVENTION
Accordingly, one embodiment of the present invention provides a lockout circuit for an operations circuit. The operations circuit is configured to receive one or more sets of inputs. Upon receiving a latching signal, the operations circuit performs a decode operation on the present set of inputs A
0
through A
n
. The decode operation, in turn, establishes a value for one or more output vectors in response to a latch signal. Further, a disable vector is included as one of the output vectors. At least one of the input sets is configured to establish a lockout value for the disable vector. Thus, once the appropriate set is input and latched, the resulting disable vector prevents inadvertent latching signals from reaching the operations circuit. However, the operations circuit is also configured to receive a reset signal and reset the disable vector in response to that signal.
In another embodiment, the operations circuit is a test vector decode circuit configured to receive a supervoltage signal. The supervoltage signal is generally maintained during all operations of the test vector decode circuit. The test vector decode circuit is configured to reset all output vectors in response to turning off the supervoltage signal. In addition, the latching signal is combined with the disable vector through logic circuitry before reaching the test vector decode circuit. Latching operations proceed as described above until the disable vector changes the logic circuitry output, thereby locking out further latching signals. Once that occurs, the output vectors will not change unless the supervoltage signal is removed. In that event, all of the test vectors would be reset and any errors in the operation of the memory circuit could more likely be traced to the interruption of the supervoltage signal rather than to inadvertent latching signals. Thus, in addition to the advantages of preventing inadvertent activation of the test mode using a minimal amount of die space, this embodiment also simplifies error detection and correction.
Still other exemplary embodiments operate similarly but use different logic circuitry configurations. Further, the test vector decode circuits in these embodiments are configured to enable latching and resetting in a manner consistent with the logic circuitry configurations.
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Brantley Charles
Micro)n Technology, Inc.
Tu Christine T.
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