Semiconductor device having LDD-type source/drain regions...

Details Semiconductor device having LDD-type source/drain regions... Semiconductor device having LDD-type source/drain regions...

2002-06-14

2004-05-18

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S300000, C438S301000

Reexamination Certificate

active

06737308

ABSTRACT:

RELATED APPLICATION
This application benefit and priority of Korean Patent Application No. 2001-33550, filed on Jun. 14, 2001, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
This disclosure relates to a semiconductor device and a method of fabricating a semiconductor device. More particularly, the disclosure will describe a semiconductor device having LDD-type source/drain regions and will also describe a method of its fabrication.
As semiconductor devices become more highly integrated, MOS transistors may be formed with shallow source/drain junction regions. In order to increase a reliability of such MOS transistors, their methods of formation may provide for LDD-type source/drain regions. The formation of the LDD-type source/drain regions may use spacers along sidewalls of a gate electrode.
A method of forming self-aligned contacts for a highly integrated semiconductor device may use silicon nitride gate spacers of high etching selectivity with respect to a silicon oxide layer.
Referring to
FIG. 1
, a device isolation layer
2
may be formed in desired regions of semiconductor substrate
1
to define an active region. An insulation layer and a gate electrode layer
5
may be formed over the surface of the semiconductor substrate. A silicon nitride capping layer
7
may then be formed on the gate electrode layer. The capping layer and the gate electrode layer may be patterned as gate electrodes over desired regions of the gate insulation layer
3
. At this time, exposed portions of the gate insulation layer
3
can be etched or may be removed by over-etching during patterning of the gate electrodes. Thus, the active regions of the substrate on both sides of the gate pattern
8
may be exposed.
Impurity ions may then be implanted into exposed regions of the active region with an implant dosage of 1×10
12
to 1×10
13
atoms/cm
2
. Gate pattern
8
may serve as an ion-implantation mask during this implant. Thus, exposed portions of the active region on both sides of the gate pattern
8
receive this low-concentration implant to define lightly doped source/drain regions
9
. Silicon nitride gate spacers
11
may then be formed against the sidewalls of gate patterns
8
. Additional impurity ions may then be implanted, but with a higher dosage of 1×10
15
to 5×10
15
atoms/cm
2
into exposed regions of the previously defined low-concentration source/drain regions
9
. The gate patterns
8
and associated gate spacers
11
may serve as ion-implantation masks during the higher dose implant, thereby forming high-concentration source/drain regions
13
. These regions
13
, accordingly, have higher impurity concentrations than that of the low-concentration source/drain regions
9
. Such low-concentration source/drain regions
9
together with the high-concentration source/drain regions
13
may be referenced together as LDD-type source/drain regions
15
.
Referring to
FIG. 2
, at the resultant surface where the LDD-type source/drain regions
15
are formed, an oxide layer may be etched to expose silicon at the surface of the substrate associated with source/drain regions. In order to decrease a resistance of an interface for a subsequent contact formation, a metal of titanium, tungsten or cobalt may be stacked over a surface of the substrate and thermally treated to form, e.g., a cobalt self aligned silicide (salicide) layer
16
in the surface layer of the substrate at locations within the source/drain regions. An etch stop layer
17
is then formed over the entire surface of the substrate including the gate. The etch stop layer
17
may comprise material having an etch selectivity with respect to (i.e., a different etch rate relative to) a silicon oxide layer.
As used herein, the terms wafer or substrate may be used to reference structures having an exposed surface for the formation of integrated circuits (IC). Substrate may include semiconductor wafers. Additionally, it may also be used to reference semiconductor structures that may be formed thereon during processing, and, thus, may include dielectric, conductive and semiconductor layers resulting from such processing. The substrate may include doped and undoped semiconductors or epitaxial semiconductor layers which may be supported by a base of semiconductor or insulator material, as well as other semiconductor structures known to one skilled in the art. Furthermore, the term conductor may include semiconductors, and the term insulator may be defined to include material less electrically conductive than the materials referred to as conductors.
Thus, width W
1
between sidewalls of the etch stop layer
17
that may cover sidewalls of the gate patterns
8
is affected in part by spacers
11
and etch stop layer
17
. Consequently, the etch stop layer
17
may be viewed as reducing the gap width W
1
and increasing an aspect ratio of the space defined between the sidewalls of the etch stop layer along gate patterns
8
. An interlayer insulation layer
19
is then formed over the entire surface of the semiconductor substrate, which now includes the etch stop layer
17
. During the formation of the insulating layer
19
, there may be a risk of a void
21
being formed within the interlayer insulation layer
19
at a region between gate patterns
8
. This risk of void formation may become greater as the etch stop layer
17
thickness affects the aspect ratio resulting between gate patterns
8
. In certain circumstances, void
21
may degrade the reliability of a semiconductor device.
Referring to
FIG. 3
, interlayer insulation layer
19
and etch stop layer
17
may be patterned to form a first contact hole
23
a
to expose a portion of metal salicide layer
16
of the LDD-type source/drain regions
15
. Additionally, second contact hole
23
b
may be formed to expose a portion of metal salicide layer
16
of the LDD-type source/drain regions
15
neighboring the device isolation layer
2
. The etch stop layer
17
may prevent recessing of the device isolation layer
2
during the formation of the contact openings. At this time, it may be difficult to expose a desired surface area of the LDD-type source/drain regions
15
(resulting from the first and second contact holes
23
a
and
23
b
as defined by the gate spacer
11
) for the formation of contacts. Particularly, as illustrated in
FIG. 3
, if a mis-alignment should occur during photolithographic processing for the formation of the first and second contact holes
23
a
and
23
b
, the surface of the LDD-type source/drain regions
15
exposed by the first contact hole
23
a
may be further decreased. Such misalignment may be more burdensome to the peripheral part. For example, at the peripheral part, the surface exposed by contact opening
23
b
may be dramatically decreased by mis-alignment. When the contact surface is decreased the contact resistance increases. It may become difficult, therefor, to achieve effective operation for such a device, even though a metal salicide may be formed at the interface.
According to the conventional process as described above, it may be difficult to obtain sufficient surface contact area to the LDD-type source/drain regions as the level of circuit integrations increase. The contact holes to be defined by gate spacers, e.g. of silicon nitride layers, may not allow sufficient width for assuring low contact resistance. Thus, it may be difficult to decrease contact resistance of semiconductor devices, especially as their level of integrations increase. Further, since the gate spacers reduce the width of the contact openings between gates, the risk of void formation may increase due to the difficulty in filling narrowed gaps with interlayer insulation material. Thus, the reliability of a semiconductor device may be compromised.
SUMMARY OF THE INVENTION
Thus, it is an object of the present invention to provide a semiconductor device which can minimize a contact resistance and also improve device reliability and to provide for methods of fabricating the same.
In one e

Affiliated with

Also associated with

Rating

Semiconductor device having LDD-type source/drain regions... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device having LDD-type source/drain regions..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having LDD-type source/drain regions... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3232618