Semiconductor integrated circuit and test pattern generation...

Details Semiconductor integrated circuit and test pattern generation... Semiconductor integrated circuit and test pattern generation...

1999-08-19

2004-01-13

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000

Reexamination Certificate

active

06678849

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit comprising flip flops (FF) and combination circuits and a test pattern generation method for generating test patterns used for detecting faulty circuits involved in the semiconductor integrated circuit.
2. Description of the Related Art
In general, a semiconductor integrated circuit comprises a plurality of flip flops (FF) and a plurality of combination circuits. Recently, there have been strong demands to provide Large Scale Integration (LSI) circuits operable in a higher frequency in the semiconductor integrated circuit field. In order to achieve this demand, the number of flip flops and the area required for the flip flops in the semiconductor integrated circuit have increased.
FIG. 1
is a block diagram showing a part of a conventional semiconductor integrated circuit. In
FIG. 1
, the reference character FF designates a flip flop,
11
a
,
11
b
,
11
c
,
11
d
, and
11
e
denote stages. Each stage comprises a plurality of the flip flops (FF). The reference characters
2
a
,
2
b
,
2
c
, and
2
d
indicate combination circuits.
There are conventional test circuit design methods such as a full scan and a partial scan in which flip flops (FF) are replaced with scan flip flop (SFF) in order to detect faulty circuits in a plurality of the flip flops (FF) and the combination circuits, and wiring defects in the semiconductor integrated circuit. The conventional test circuit design methods use an Auto Test Pattern Generation (ATPG) to generate test patterns automatically.
FIG. 2
is an explanation circuit showing a full scan test method. In
FIG. 2
, the reference characters
12
a
,
12
b
,
12
c
,
12
d
, and
12
e
designate stages. The reference number
12
denotes a scan chain through which test patterns are transferred from an external device such as an external tester (not shown) to the scan flip flops (SFF) in each stage. That is, through the scan chain
12
, the scan flip flops (SFF) in the stages
12
a
to
12
e
are connected in series. Other circuit components shown in
FIG. 2
are the same as the circuit components in the semiconductor integrated circuit shown in FIG.
1
. Therefore the same reference characters are used for the same components.
Next, a description will be given of the operation of the conventional test pattern generation method.
In the full scan method, the scan chain
12
is formed by connecting the scan flip flops (SFF) in the stage
12
a
,
12
b
,
12
c
,
12
d
, and
12
e
in series. During the scan mode, the test pattern is set into the scan flip flops (SFF) through the scan chain
12
. During a normal mode after this scan mode, a clock signal is supplied so that the combination circuits
2
a
,
2
b
,
2
c
, and
2
d
input the test pattern from the scan flip flops (SFF) in each of the stages
12
a
,
12
b
,
12
c
,
12
d
, and
12
e
and then output the test patterns. Further, during the scan mode after this normal mode, the scan flip flops (SFF) in each stage input the test pattern from the combination circuits
2
a
,
2
b
,
2
c
, and
2
d
. After this, the external tester (not shown) monitors the test result obtained by the above test operation to detect the presence or absence of circuit defects or wiring defects in the semiconductor integrated circuit.
FIG. 3
is a flow chart showing the procedure of the full scan method.
First, the combination circuits
2
a
,
2
b
,
2
c
, and
2
d
in the semiconductor integrated circuit are extracted (Step ST
131
). Next, the ATPG is executed for the combination circuits
2
a
,
2
b
,
2
c
, and
2
d
(Step ST
132
). Since the test pattern generated by the ATPG controls the input to and output from each of the combination circuits
2
a
,
2
b
,
2
c
, and
2
d
, it cannot be directly used for the test of an actual semiconductor integrated circuit.
Next, the formatting of the test pattern generated by the ATPG is executed in order to use the test pattern for the actual semiconductor integrated circuit (Step ST
133
). For example, in the formatting of the test pattern used for testing of the combination circuit
2
a
, the test pattern is set into the scan flip flop (SFF) in the first stage
12
a
through the scan chain
12
. After this, during the normal operation mode, the scan flip flops (SFF) in the stage
12
b
input the output from the combination circuit
2
a
during one system clock. Finally, the data stored in the scan flip flops (SFF) in the stage
12
b
are transferred to the external device such as the external tester (not shown) through the scan chain
12
during the scan operation mode.
In general, the above described operations are repeated required times for the formatting of the test patterns because the ATPG generates many test patterns. In this case, the test patterns may be generated only for small scale combination circuits that are divided by the scan chain
12
. Accordingly, the test patterns are relatively generated and it is possible to increase the rate of the detection of faulty circuits by using the small scale test patterns.
However, the circuit area of the semiconductor integrated circuit is increased because all of the flip flops in the semiconductor integrated circuit are replaced with the scan flip flops in the full scan method. The rate of the increasing of the area is proportional to the number of the flip flops.
The difference in area between the flip flop (FF) and the scan flip flop (SFF) will be explained.
FIG. 4
is a block diagram showing a configuration of a flip flop (FF).
FIG. 5
is a block diagram showing a configuration of a scan flip flop (SFF). In FIG.
4
and
FIG. 5
, the reference character D designates a data input line through which a data item is inputted, and SI denotes an input data line through which a scan data item is inputted. The reference character SM in
FIG. 5
denotes a control line through which a control signal to set the scan flip flop (SFF) into the scan operation mode is inputted. The reference character T designates an input line through which a scan clock is inputted. This scan clock controls the operation of the scan flip flop (SFF). The reference character Q indicates an output line through which the data is outputted. The reference character QC designates an output line through which an inverted data item that is obtained by inverting the level of the data on the output line Q is outputted.
As clearly shown in FIG.
4
and
FIG. 5
, the scan flip flop (SFF) shown in
FIG. 5
is larger in circuit size than the flip flop (FF) shown in FIG.
4
. That is, the scan flip flop (SFF) shown in
FIG. 5
has a larger circuit area when compared with the flip flop (FF).
Recently, there have been strong demands to provide a semiconductor integrated circuit operable in a high frequency. In order to achieve this demand, the number of stages made up of combination circuits must be decreased. Each of the combination circuits are placed between stages made up of flip flops (FF). This means an increase in the number of the flip flops (FF). Accordingly, the application of the full scan to a semiconductor integrated circuit introduces a drawback that the overhead of the circuit area in the semiconductor integrated circuit is increased because all of the flip flops (FF) must be replaced with the scan flip flops (SFFs) in the full scan.
FIG. 6
is a diagram explaining a procedure of a partial scan operation. In
FIG. 6
, the reference characters
16
a
,
16
b
,
16
c
,
16
d
, and
16
e
designate stages. The stages other than the stage
16
c
include both flip flops and scan flip flops. In the configuration shown in
FIG. 6
, all of the scan flip flop (SFF) are connected to each other through a scan chain
16
. Other circuit components shown in
FIG. 6
are the same of the circuit components of the semiconductor integrated circuit shown in FIG.
1
. Accordingly, the same reference characters are used for the same circuit components.
Next, a description will be given of the operation of the partial scan.
FIG. 7
is a flowchart showin

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