Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-15
2004-04-20
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S262000, C438S954000
Reexamination Certificate
active
06723605
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to semiconductor technology and more specifically to shallow trench isolation and bitline integration in MirrorBit® Flash memory.
2. Background Art
Various types of memories have been developed in the past as electronic memory media for computers and similar systems. Such memories include electrically erasable programmable read only memory (EEPROM) and electrically programmable read only memory (EPROM). Each type of memory had advantages and disadvantages. EEPROM can be easily erased without extra exterior equipment but with reduced data storage density, lower speed, and higher cost. EPROM, in contrast, is less expensive and has greater density but lack erasability.
A newer type of memory called “Flash” EEPROM, or Flash memory, has become extremely popular because it combines the advantages of the high density and low cost of EPROM with the electrical erasability of EEPROM. Flash memory can be rewritten and can hold its contents without power. It is used in many portable electronic products, such as cell phone, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc.
In Flash memory, bits of information are programmed individually as in the older types of memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips. However, in DRAMs and SRAMs where individual bits can be erased one at a time, Flash memory must currently be erased in fixed multi-bit blocks or sectors.
Conventionally, Flash memory is constructed of many Flash memory cells where a single bit is stored in each memory cell and the cells are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. However, increased market demand has driven the development of Flash memory cells to increase both the speed and the density. Newer Flash memory cells have been developed that allow more than a single bit to be stored in each cell.
One memory cell structure involves the storage of more than one level of charge to be stored in a memory cell with each level representative of a bit. This structure is referred to as a multi-level storage (MLS) architecture. Unfortunately, this structure inherently requires a great deal of precision in both programming and reading the differences in the levels to be able to distinguish the bits. If a memory cell using the MLS architecture is overcharged, even by a small amount, the only way to correct the bit error would be to erase the memory cell and totally reprogram the memory cell. The need in the MLS architecture to precisely control the amount of charge in a memory cell while programming also makes the technology slower and the data less reliable. It also takes longer to access or “read” precise amounts of charge. Thus, both speed and reliability are sacrificed in order to improve memory cell density.
An even newer technology allowing multiple bits to be stored in a single cell is known as “MirrorBit®” Flash memory has been developed. In this technology, a memory cell is essentially split into two identical (mirrored) parts, each of which is formulated for storing one of two independent bits. Each MirrorBit Flash memory cell, like a traditional Flash cell, has a gate with a source and a drain. However, unlike a traditional Flash cell in which the source is always connected to an electrical source and the drain is always connected to an electrical drain, each MirrorBit Flash memory cell can have the connections of the source and drain reversed during operation to permit the storing of two bits.
The MirrorBit Flash memory cell has a semiconductor substrate with implanted conductive bitlines. A multilayer storage layer, referred to as a “charge-trapping dielectric layer”, is formed over the semiconductor substrate. The charge-trapping dielectric layer can generally be composed of three separate layers: a first insulating layer, a charge-trapping layer, and a second insulating layer. Wordlines are formed over the charge-trapping dielectric layer perpendicular to the bitlines. Programming circuitry controls two bits per cell by applying a signal to the wordline, which acts as a control gate, and changing bitline connections such that one bit is stored by source and drain being connected in one arrangement and a complementary bit is stored by the source and drain being interchanged in another arrangement.
Programming of the cell is accomplished in one direction and reading is accomplished in a direction opposite that in which it is programmed.
One significant problem in memory devices is that the implanted conductive bitlines have a relatively high resistivity, which results in higher power requirements, and subsequent heat generation with reduced life expectancy, for the memory cell.
A second significant problem involves the large number of steps needed to form shallow trench isolation (STI). STI is used to electrically isolate the MirrorBit memory in the core region from the other devices in the peripheral area. It consists of trenches filled with an insulator material, such as silicon oxide, forming an electrical barrier to prevent interference between core and peripheral devices. Unfortunately, traditional STI construction requires a large number of processing steps, which are performed separately from those used to create devices in the core. With the prohibitive cost in equipment, time, and planning for each additional step, it is crucial to minimize the number of process steps.
A third significant problem is that, during implantation of the bitlines, dopant is subject to a scattering effect. The impact of the dopant on and in the semiconductor substrate causes the dopant ions to scatter at angles away from the direction of implantation so the ions not end up directly under the implantation region. As a result, when the bitline and dopant are annealed, the dopant diffuses over a wider region than desired. This severely limits how closely the bitlines can be placed and, thus, how small the memory device can be made.
A solution that would solve the above and other problems with implanted bitlines has been long sought but has long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides a method for manufacturing a Flash memory with high conductivity bitlines and shallow trench isolation integration. A hard mask layer is deposited over a substrate. A first photoresist is deposited over the hard mask layer, processed, and used to form a hard mask. The first photoresist is removed and the substrate is processed using the hard mask to form a core trench and a shallow trench isolation (STI) trench. The trenches are filled with an insulating material in an STI fill process. A second photoresist is deposited and processed to form a core mask over the STI trenches. Using the core mask, the insulating material is removed from the core trenches and the core mask is removed. A doped bitline material is deposited on the surface of the semiconductor, which fills the core trench. The surface of the semiconductor is planarized, inlaying insulating material and doped bitline material in the trenches. A thermal anneal outdiffuses the dopant from the doped bitline material into the substrate.
The present invention further provides high conductivity bitlines for Flash memory and a manufacturing method therefor.
The present invention also provides a method for manufacturing Flash memory, which integrates STI and bitline creation, resulting in fewer process steps.
REFERENCES:
patent: 5635415 (1997-06-01), Hong
patent: 6071779 (2000-06-01), Mehrad et al.
patent: 6207493 (2001-03-01), Furukawa et al.
patent: 6242305 (2001-06-01), Foote et al.
patent: 6326268 (2001-12-01), Park et al.
patent: 2002/0039821 (2002-04-01), Wolstenholme
Erhardt Jeffrey P.
Sahota Kashmir S.
Advanced Micro Devices , Inc.
Booth Richard A.
Ishimaru Mikio
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