Method of forming fine patterns of semiconductor device

Details Method of forming fine patterns of semiconductor device Method of forming fine patterns of semiconductor device

2003-05-19

2004-04-20

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C438S258000, C438S587000

Reexamination Certificate

active

06723607

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of forming a semiconductor device. More particularly, the present invention is directed to a method of forming fine patterns of a semiconductor device.
BACKGROUND OF THE INVENTION
A semiconductor device is formed of material patterns of several types. Forming the material patterns includes etching a lower layer stacked on a semiconductor substrate by using a photoresist pattern as an etch mask. Forming the photoresist pattern includes an exposure process typically using a light having a wavelength of several hundred nanometers. A line width of the pattern, which can be realized by the exposure process, depends on the wavelength of the light. Accordingly, the line width of the material pattern, which can be realized by the typical exposure process, suffers from this limitation.
To solve the foregoing problem, another patterning method using a spacer as an etch mask has been proposed.
FIG. 1
is a top plan view showing a prior art patterning method using a spacer as an etch mask.
FIGS. 2A through 2C
are cross-sectional views taken along a dotted line II—II of FIG.
1
. Referring to
FIG. 2A
, a lower layer
20
and a sacrificial pattern
30
are sequentially formed on a semiconductor substrate
10
. Here, the sacrificial pattern
30
is formed by typical photolithography and etching processes. A spacer insulating layer
40
is conformally formed over an entire surface of the semiconductor substrate including the sacrificial pattern
30
. As shown in
FIG. 2B
, the spacer insulating layer
40
is anisotropically etched to form spacers
45
around sidewalls of the sacrificial pattern
30
. As shown in
FIG. 2C
, the sacrificial pattern
30
is removed to expose the lower layer
20
. Thereafter, the lower layer
20
is etched by using the spacers
45
as an etch mask. Thus, lower patterns
25
are formed under the spacers
45
.
As illustrated in
FIG. 1
, in the event that the sacrificial pattern
30
has a bar shape, each spacer
45
and lower pattern
25
make a closed loop. Thus, to use the lower pattern
25
in the semiconductor device as a conductor between two or more points, an additional patterning process for removing a predetermined region of the lower pattern
25
is performed such that the lower pattern
25
forms an open loop or line.
FIG. 3
illustrates a top plain view showing a similar patterning method, and
FIG. 4
is a cross-sectional view taken along line IV—IV in FIG.
3
. As illustrated in
FIG. 3
, the additional patterning process is also needed when a sacrificial pattern
35
with a bar-shaped opening is formed. In this case, as illustrated in
FIGS. 3 and 4
, the spacer
45
will form the closed loop to surround the inner sidewalls of the sacrificial pattern
35
. Therefore, for the same reason, it is necessary to perform the additional patterning process to obtain an open loop or line.
SUMMARY OF THE INVENTION
In the method of forming fine patterns of a semiconductor integrated circuit, a mask layer is formed over a semiconductor structure having a first region and a second region. A portion of the mask layer over the first region is removed to expose the semiconductor structure, and sacrificial layer patterns are formed over the exposed semiconductor structure. Then, spacers are formed on sidewalls of the sacrificial layer patterns and the mask layer, and portions of the spacers are removed to create fine mask patterns. The semiconductor structure is then patterned using the fine mask patterns to create fine patterns.
By using the mask layer to create exposed region where the sacrificial layer patterns are formed, the sacrificial layer patterns are formed to a same height as the mask layer. If applications of the present invention involve forming patterns from the mask layer, then this further results in the fine mask patterns and the mask layer patterns being at substantially a same height.


REFERENCES:
patent: 5747359 (1998-05-01), Yuan et al.
patent: 6337262 (2002-01-01), Pradeep et al.
patent: 6613621 (2003-09-01), Uh et al.
Michael S. Hibbs; “IBM Microelectronic Divison”; pp. 104-105; ©1998.

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