Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Amorphous semiconductor
Reexamination Certificate
2001-06-11
2004-05-04
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Amorphous semiconductor
C438S653000, C438S253000
Reexamination Certificate
active
06730581
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a MOS device, such as a MOS transistor or a MOS capacitor, and more specifically to a semiconductor device containing MOS devices having their respective gate electrodes made of a metal or metal compound and a method of manufacture thereof.
In recent years, as a key component of computers and communications equipment use is extensively made of a large-scale integrated circuit or circuits (LSI circuits) in which a very large number of transistors and resistors are integrated into a single chip so that they are interconnected to implement electronic circuitry. For this reason, the performance of the whole equipment depends largely on the performance of the LSI circuit. The performance of the LSI circuit can be upgraded by increasing the packing density, namely, scaling down the dimensions of the MOS devices (microstructuring of the MOS devices).
For example, in the case of MOS transistors, the microstructuring of devices can be realized by reducing the gate length and making source/drain diffusion layers small in thickness.
As a method of forming shallow source/drain diffusion layers, low-acceleration ion implantation is widely used, by which source/drain diffusion layers having a thickness of less than 0.1 &mgr;m can be formed.
However, the source/drain diffusion layers formed by the low-acceleration ion implantation have a high sheet resistance as high as 100&OHgr;/□. Thus, an increase in the speed of circuit operation owing to microstructuring cannot be expected without modification.
With devices having high speed requirements, such as logic LSI circuits, the salicidation technology is used by which a silicide film is formed on source/drain diffusion layers and the top of the gate electrode made of a polycrystalline silicon (hereinafter referred to as polysilicon) film doped with impurities using a self-aligned process.
In the formation of dual-gate MOS transistors (n-channel and p-channel MOS transistors formed in the same substrate: the n-channel transistor has a gate electrode made of n-type doped polysilicon and the n-channel transistor has a gate electrode made of p-type doped polysilicon), the salicidation technology can effect not only a reduction in the resistance of gate electrodes but also a decrease in the number of manufacturing steps.
The reason is that, in the ion implantation step of forming source/drain diffused regions, the gate can be doped with impurities of given conductivity type.
In contrast, in the formation of dual-gate MOS transistors having a polycide (polysilicon-silicide) gate electrode in which a metallic silicide film is formed onto a polysilicon film doped with impurities, the polysilicon film cannot be doped with impurities of given conductivity type in the ion implantation step for forming source/drain regions because it is masked by the metallic silicide film.
Therefore, prior to the formation of source/drain regions it is required to dope the polysilicon film with impurities of given conductivity type. That is, the ion implantation step for forming the source/drain regions and the ion implantation step for doping the polysilicon film with impurities have to be carried out separately, increasing the number of steps.
To be specific, in comparison with the salicide process, the polycide process requires two additional steps for each of photolithography, ion implantation, and resist stripping.
On the other hand, with devices that require devices to be packed as closely as possible as in memory LSI circuits such as DRAMs, it is essential to adopt SAC (Self-Aligned Contact) structures.
The formation of the SAC structure involves a step of etching an interlayer insulating film on one of the source/drain diffusion layers (usually one used as the source) by means of RIE (Reactive Ion Etching) to form a contact hole to the source/drain diffusion layer.
At this point, even if the contact hole is misaligned, it is required not to expose the top of the polysilicon gate electrode. To this end, a silicon nitride film is formed in advance on the gate electrode as an etching stopper film.
The presence of such a silicon nitride film will not allow impurities to be introduced into the gate electrode in the ion implantation step for the formation of the source/drain regions. For this reason, unlike the logic LSI, in the memory LSI, the salicidation technology cannot be used.
Heretofore, gate electrodes made of impurity-doped polysilicon (polysilicon gate electrodes) have been widely used. In addition, the polycide gate electrodes have also been used to comply with low-resistivity requirements.
Where gate electrodes of much lower resistivity are required, a poly-metal gate electrode structure is used in which an impurity-doped polysilicon film, a barrier metal film and a tungsten (W) film are stacked in sequence. The poly-metal gate electrode, which is lower in resistivity than the polycide gate electrode, can implement a desired sheet resistance with reduced film thickness.
However, the poly-metal electrode has the following problem: As described previously, the dual-gate structure is used in logic LSI circuits. As with the use of the polycide gate structure, the use of the poly-metal gate electrode structure in logic LSI circuits requires two separate steps: a step of ion implanting impurities into the polysilicon film of the poly-metal gate electrode, and a step of ion implanting impurities into the silicon substrate to form the source/drain regions. This thus results in an increase in the number of steps and an increased in manufacturing cost.
In an LSI circuit having a logic IC and a DRAM built in, the formation of a silicide film onto the top of the source/drain diffusion layers in the DRAM results in an increase in the current leakage in pn junctions of memory cells, degrading the data holding property of the cells. In the DRAM, which requires the SAC structure as described previously, a W polycide electrode is used.
On the other hand, for the DRAM to allow as much current as possible to flow with a low voltage, it is required to lower the threshold voltage of MOS transistors. To this end, it is required to dope the polysilicon film in the gate electrodes of n-channel MOS transistors with n-type impurities such as phosphorous (P) or arsenic (As) and dope that of p-channel MOS transistors with p-type impurities such as boron (B).
Here, in the DRAM, the thermal budget (determined by time and temperature) after the formation of the gate electrodes is great. Therefore, the use of the polysilicon films doped with such impurities for gate electrodes (polycide gate electrodes) poses two problems in the thermal process subsequent to the formation of the gate electrodes.
The first problem results from that, in the thermal process subsequent to the formation of the gate electrodes, the impurities, such as P or As, doped into the polysilicon film diffuse outward into the W silicide film and results in a decrease in the impurity concentration in the polysilicon film.
When the impurity concentration in the polysilicon film is decreased, the depletion layer spreads into the gate electrode when it is impressed with a gate voltage. As a result, the actual gate capacitance becomes smaller than the gate capacitance defined by the gate insulating film by the amount corresponding to the depletion layer. That is, the first problem is that the threshold voltage of the MOS transistors deviates from the designed value.
The second problem results from that, in the thermal process subsequent to the formation of the gate electrodes, the impurities, such as B, penetrate through the gate oxide into the silicon substrate.
The penetration of B through the gate oxide into the silicon substrate results in a change in the distribution of impurity concentration in the channel region. In this case as well, the problem arises in that the threshold voltage deviates from the designed value.
The penetration of B (inward diffusion of B) is promoted by doping the gate oxide with fluorine (F) or hydrogen (H) but controlled by dop
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Jr. Carl Whitehead
Kabushiki Kaisha Toshiba
Schillinger Laura M
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