Static information storage and retrieval – Systems using particular element – Semiconductive
Reexamination Certificate
2001-06-12
2004-01-20
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Semiconductive
C365S149000, C365S187000, C365S189011
Reexamination Certificate
active
06680864
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor memory devices. More particularly, it pertains to a vertical gain cell and array for a dynamic random access memory and method for forming the same.
BACKGROUND OF THE INVENTION
Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits and memory cells. The functional demands placed on these circuits and memory cells require the use of an ever-increasing number of linked transistors. As the number of transistors required increases, the surface space on the silicon chip/die that is allocated to each transistor dwindles. It is desirable then, to construct transistors which occupy less surface area on the silicon chip/die.
Typically, the memory cells of dynamic random access memories (DRAMs) include two main components, a field-effect transistor (FET) and a capacitor which functions as a storage element. The need to increase the storage capability of semiconductor memory devices has led to the development of very large scale integrated (VLSI) processes capable of creating smaller and smaller features. This reduction of feature size provides a substantial increase in density of memory cells in a DRAM.
The effort of extending DRAM cell density beyond the 1 gigabit generation presents the challenge of providing adequate cell capacitance within the projected cell area. Since capacitance is directly related to the surface area of the capacitor's plates, decreasing feature sizes make it very difficult to maintain sufficient cell capacitance. A cell capacitance of greater than or equal to twenty-five femto farads (≧25 fF) is typically required in order to provide an adequate signal for sensing the stored charge over and above the anticipated noise levels. As memory cells are constructed to save precious chip space, they need to be configured in such a manner that the same data information can be stored and accessed.
An attractive means of maintaining the required storage ability is to implement a gain cell which provides an output current rather than a charge. Current sensing offers greater noise immunity and faster operation times than the conventional charge sense amplifier latch. One approach to this has been to provide a conventional, planar one transistor DRAM cell configuration to store charge on a planar diffused junction storage node. This node acts in turn as the gate of a lateral junction field-effect transistor (JFET) which is used to read the cell charge state.
An alternate approach is to construct a vertical cell with a surrounding gate write device wherein access to a read JFET is through a forward biased junction with the write bit line contact. The drawback to this method is that the forward biased junction causes the injection of minority carriers into the JFET channel which will then be collected largely by the storage node junction. Thus, the read operation of this device is destructive and transient.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory cell structure for dynamic random access memory devices which provide increased cell density while maintaining adequate cell capacitance and charge retention times. There is further need for such a memory cell structure offering these advantages along with a non-destructive read function.
SUMMARY OF THE INVENTION
In one embodiment, a gain cell is provided. The gain cell includes a write transistor having multiple sides and a read transistor having multiple sides. The write transistor has a body region and first and second source/drain regions. The write transistor also has a gate that is associated with a first side of the write transistor. Similarly, the read transistor has a gate region, a body region and a first and second source/drain regions. The read transistor and the write transistor are formed in a vertical pillar of single crystalline semiconductor material the extends outwardly from a semiconductor substrate. A charge storage node surrounds a portion of the pillar adjacent to the second source/drain region of the write transistor. There is a write bit line coupled to the first source/drain region of the write transistor. A write wordline is coupled to the gate of the write transistor. A read bit line is coupled to the body region of the write transistor. And, a read wordline is coupled to second source/drain region of the read transistor.
In another embodiment, a gain cell is provided which has an n-channel transistor and a p-channel transistor. Both transistors have multiple sides. The n-channel vertical transistor has a body region and first and second source/drain regions. The n-channel transistor also has a gate that is associated with a first side of the n-channel transistor. Similarly, the p-channel transistor has a gate region, a body region and first and second source/drain regions. The n-channel transistor and the p-channel transistor are formed in a vertical pillar of single crystalline semiconductor material that extends outwardly from a semiconductor substrate. A charge storage node that surrounds a portion of the pillar adjacent to the second source/drain region of the n-channel transistor. There is a write bit line coupled to the first source/drain region of the n-channel transistor. A write wordline is coupled to the gate of the n-channel transistor. A read bit line is coupled to the body region of the n-channel transistor. And, a read wordline is coupled to second source/drain region of the p-channel transistor.
In another embodiment, a memory array on a substrate is provided. The memory array includes multiple vertical pillars of single crystalline semiconductor material extending outwardly from the substrate. The pillars have multiple sides, and each pillar includes a pair of transistors in the same pillar. Each of the transistors has a body region, a gate region and first and second source/drain regions. The second source/drain region of a first transistor comprises the gate for a second transistor. The first source/drain region of the second transistor comprises the body region of the first transistor. The pillars form an array of rows and columns. There are a number of write wordlines, wherein each write wordline is coupled to the gates of the first transistors in a row of vertical pillars in the array. A number of write bit lines are provided such that each write bit line is coupled to the first source/drain regions of the first transistors in a column of vertical pillars in the array. A charge storage node is coupled to the second source/drain region of each first transistor in the array of vertical pillars. There are also provided a number of read bit lines, such that each read bit line is coupled to the first source/drain regions of the second transistors in a row of vertical pairs in the array. A number of read wordlines are included such that each read wordline is coupled to the second source/drain regions of the second transistors in a column of vertical pillars in the array.
In another embodiment, a data storage device is provided. The data storage device includes a memory array having a plurality of gain cells. The memory array further includes multiple vertical pillars of single crystalline semiconductor material extending outwardly from the substrate. The pillars have multiple sides. Each pillar includes a pair of transistors in the same pillar. The transistors have a body region, a gate region and first and second source/drain regions. The second source/drain region of a first transistor comprises the gate for a second transistor, and the first source/drain region of the second transistor comprises the body region of the first transistor. The pillars form an array of rows and columns which also include a number of write wordlines, a number of write bit lines, a charge storage node on each pillar, a number of read bit lines, and a number of read wordlines.
Each write wordline is coupled
Dinh Son T.
Schwegman Lundberg Woessner & Kluth P.A.
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