Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-09-27
2004-05-11
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S706000, C438S712000
Reexamination Certificate
active
06734108
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the fabrication of integrated circuits, and more particularly to the formation of contacts in an integrated circuit.
BACKGROUND OF THE INVENTION
Most integrated circuit (IC) manufacturing processes typically include a number of manufacturing steps. Such steps may form, shape or otherwise modify a material, such as a conductive, semiconductive and/or insulating material, and thereby create an IC device.
It can be desirable to reduce the number of steps in a manufacturing process. Such a reduction in process steps may have a number of beneficial results. The complexity of the overall manufacturing process may be reduced, making the fabrication of an IC easier to accomplish. A process yield may be increased, as the elimination of one or more steps may translate into fewer chances of forming defects. An IC may be fabricated in a shorter time period (cycle time is reduced). This can reduce the overall cost and/or increase manufacturing capacity.
The elimination of particular IC manufacturing process steps may have other benefits. For some integrated circuits, it may be desirable to minimize an IC's exposure to temperature cycles (keeping as small a “thermal budget” as possible). Too many temperature cycles in a fabrication process may undesirably alter properties of structures formed within an IC. As just a few examples, if an IC includes metal-oxide-semiconductor (MOS) field effect transistors (FET), exceeding a thermal budget may result in shifts in the threshold voltage (Vt) of such transistors. The reliability of such transistors may also be adversely affected, as transistor junctions may be more susceptible to failure mechanisms such as junction breakdown or “punch-through” current.
If an integrated circuit includes metal contacts to a doped semiconductor substrate, temperature cycles may result in higher contact resistance due to segregation of dopants at the metal-semiconductor interface and/or increased oxidation of the metal.
If an integrated circuit includes a substrate with diffusion regions formed with dopants, temperature cycles may increase diffusion region features due to out-diffusion of dopants.
Accordingly, reductions in the number of temperature cycles in an IC manufacturing process may produce more robust devices, avoid higher contact resistance, and/or allow for smaller device features.
Integrated circuits can typically include various layers of conductive and/or semiconductive materials (referred to herein collectively as “conducting” materials), as well as insulating materials. For example, an integrated circuit may include a substrate in which a number of active devices (such as transistors) may be formed. Such active devices may then be connected to one another by one or more conducting layers. The interconnecting conducting layers may be separated from one another by insulating layers.
A conducting layer may be formed from a single layer of material, or alternatively, include one or more conducting materials. As just a few examples, such a layer can include a conventionally doped polycrystalline silicon (polysilicon) and “silicide” (silicon-metal alloy). Alternatively, a conducting layer may include a titanium(Ti)-tungsten(W) alloy layered onto bulk aluminum, with an underlying barrier layer comprising Ti, Ti-nitride (TiN), or a Ti alloy.
Similarly, insulating layers can also be composites. As just one example, an insulating layer may include a “doped” silicon dioxide (“oxide”) and an “undoped” silicon oxide (undoped silicate glass or “USG”). The doped silicon oxide can include dopant elements, such as boron and phosphorous, while the undoped silicon oxide can be essentially free of dopant elements. Phosphorous doped silicon dioxide (phosphosilicate glass or “PSG”) can provide advantageous ion gettering and/or step coverage properties. Boron and phosphorous doped silicon dioxide (borophosphosilicate glass or “BPSG”) can also provide such advantages, and can be formed at lower temperatures, and thus can result in a more desirable thermal budget.
An insulating layer may perform a variety of functions in an integrated circuit. For example, an insulating layer may serve to electrically isolate one conducting layer or structure from another. Further, an insulating layer may serve as the surface on which subsequent layers are formed and patterned. Therefore, in many cases it may be desirable for an insulating layer to provide a relatively planar surface.
Different conducting layers may be connected to one another and/or to a substrate by contacts and/or vias. Contacts and/or vias can include contact holes that extend through one or more insulating layers. Conventionally, a contact may connect a conducting portion of a substrate to a conducting layer, while a via may connect two different conducting layers to one another.
A conventional way of forming a contact hole in one or more insulating layers may include lithography and etch steps. Lithography can be used to form an etch pattern over an insulating layer (that includes the location of contact holes). An etch step can transfer the pattern onto one or more lower situated insulating layers.
One concern with certain contact structures can be the alignment of a contact with a lower conducting layer. Because a contact is usually formed by etching a hole through an insulating layer to an underlying conducting layer or structure, it is desirable that an etched hole to be aligned over the desired contact location in the lower conducting layer.
Further, it may be desirable to ensure that a contact hole is sufficiently insulated from other conductive lines. For example, in the case of semiconductor devices having insulated gate field effect transistors (IGFETs), such as metal-oxide-semiconductor FETs (MOSFETs), it is desirable to have a contact hole aligned with a source or drain, but at the same time, be sufficiently insulated from a conducting gate structure. A common approach to aligning contacts to conducting gate structures is a “self-aligned” contact. A self-aligned contact may include a lower conducting structure (such as a transistor gate) that includes a top insulating layer and a side insulating layer (such as a “sidewall”). With such an arrangement, a contact hole can be etched without a minimum spacing requirement with respect to the lower conducting structure.
Another concern regarding, contacts and/or vias is contact area. The area of a contact can be of concern as a substrate on which a contact is formed may also include other important features, such as transistor channels, transistor isolation structures, transistor diffusion regions, and/or device wells. Thus, reductions in contact size can provide more area for other features and/or reduce the overall size of an integrated circuit device. Further, in many processes, contact area may have a minimum requirement in order to ensure a low enough contact resistance value. Thus, it is desirable that a contact forming process be capable of meeting a minimum contact resistance value.
Various factors may contribute to reducing contact area. In the case of “self-aligned” contacts, sidewalls and/or other structures, such as “etch” stop layers, may encroach on a contact area. Another factor is that of contact aspect ratio (AR). An aspect ratio can describe the ratio between a contact height and width, when viewed in cross section. The higher the aspect ratio, the more difficult it may be to form the contact.
To better understand the formation of certain integrated circuit structures, including contacts structures, a conventional self-aligned contact (SAC) approach is set forth in
FIGS. 7A-7H
.
FIGS. 7A-7H
set forth a number of side cross-sectional views of a portion of an integrated circuit.
FIG. 7A
shows a substrate
700
on which may be formed conducting structures
702
. A conducting structure
702
may be the gate of an insulated gate field effect transistor, such as a MOSFET. A substrate
700
many include doped monocrystalline silicon having various diffusion regions (not shown) formed the
Jin Bo
Qiao Jianmin
Sharifzadeh Shahin
Cypress Semiconductor Corporation
Norton Nadine G.
Sako Bradley T.
Umez-Eronini Lynette T.
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