Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-26
2004-05-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S416000, C438S418000
Reexamination Certificate
active
06737324
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 91114489, filed Jul. 01, 2002.
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a method for fabricating a semiconductor device.
More particularly, the present invention relates to a method for fabricating a raised source/drain of a semiconductor device.
2. Description of Related Art
Except a gate oxide layer and a gate structure, a metal-oxide-semiconductor (MOS) device also comprises a source/drain region in the substrate beside the gate structure. The source/drain region has a conductivity type different from that of the substrate. In the field of VLSI, MOS devices are widely used in various circuits, such as logical circuits and memory circuits, and are essential for the devices.
Refer to FIGS.
1
A~
1
C, which illustrate a process flow of fabricating a MOS device in the prior art in a cross-sectional view.
Refer to
FIG. 1A
, a substrate
100
is provided. Then, a thin oxide layer
102
and a polysilicon layer
104
are sequentially formed on the substrate
100
.
Refer to
FIG. 1B
, the polysilicon layer
104
and the thin oxide layer
102
are patterned to form a gate conductive layer
104
a
and a gate oxide layer
102
a
, respectively. An implantation is then performed to form a source/drain extension
108
in the substrate
100
beside the gate conductive layer
104
a
by using
104
a
as a mask.
Refer to
FIG. 1C
, a spacer
110
is formed on the sidewalls of the gate conductive layer
104
a
. An implantation is performed to form a source/drain
112
in the substrate
100
beside the spacer
110
with the gate conductive layer
104
a
and the spacer
110
as a mask.
The area of the source/drain region in a semiconductor device must be reduced as the device is miniaturized for higher integration. However, the miniaturization of the source/drain region increases the resistance, so the device current is decreased to cause overloading. The overloading problem can be solved by increasing the junction depth of the source/drain, but such a method results in the short channel effect and junction leakage. On the other hand, the source/drain can be formed with a shallow junction and a high dopant concentration, instead of a deeper junction, to prevent overloading, short channel effect and junction leakage simultaneously. However, the high-concentration strategy is usually not effective in preventing overloading because of the restriction of the solid state solubility. Furthermore, a method is provided in the prior art that decreases the spacer width and forms a shallow junction to prevent overloading and short channel effect. Unfortunately, the metal silicide layer on the source/drain with a shallow junction may cause unacceptable junction leakage.
SUMMARY OF INVENTION
Accordingly, this invention provides a method for fabricating a raised of a semiconductor device to lower the resistance of the source/drain.
This invention also provides a method for fabricating a raised source/drain of a semiconductor device to makes it feasible to form a source/drain with a shallow junction, so as to prevent the short channel effect and junction leakage.
A method for fabricating a raised source/drain of a semiconductor device of this invention is described as follows. A gate structure that comprises a gate oxide layer and a gate conductive layer is formed on a substrate. A low-energy implantation is used to form a source/drain with a shallow-junction in the substrate beside the gate structure, wherein the implanting energy is, for example, 2~3 KeV. Thereafter, a spacer is formed on the sidewalls of the gate structure. An elevated SiGe layer is formed on the gate structure and the source/drain with a shallow junction, wherein the SiGe layer on the source/drain serves as a raised source/drain of the device. The elevated SiGe layer is formed with rapid thermal chemical vapor deposition (RTCVD) using a reaction gas of Si
2
H
6
/GeH
4
mixture or SiH
2
Cl
2
/GeH
4
mixture. An implantation is performed to dope the elevated SiGe layer with P-type ions or N-type ions, and then a rapid thermal process (RTP) is conducted to anneal the elevated SiGe layer. A metal silicide layer is formed on the elevated SiGe layer to lower the resistance of the device.
Another method for fabricating a raised source/drain of a semiconductor device of this invention is described as follows. A gate structure that comprises a gate oxide layer, a gate conductive layer and a capping layer thereon is formed on a substrate. A low-energy implantation is used to form a source/drain with a shallow-junction in the substrate beside the gate structure, wherein the implanting energy is, for example, 2~3 KeV. Thereafter, a spacer is formed on the sidewalls of the gate structure. An elevated SiGe layer is formed on the source/drain with a shallow junction, wherein the SiGe layer on the source/drain serves as a raised source/drain of the device. The elevated SiGe layer is formed with rapid thermal chemical vapor deposition (RTCVD) using a reaction gas of Si
2
H
6
/GeH
4
mixture or SiH
2
Cl
2
/GeH
4
mixture. An implantation is performed to dope the elevated SiGe layer with P-type ions or N-type ions, and then a rapid thermal process (RTP) is conducted to anneal the elevated SiGe layer. A metal silicide layer is formed on the elevated SiGe layer to lower the resistance of the device. In this method, the capping layer and the spacer may comprise the same material or different materials. If the capping layer and the spacer comprise different materials, the metal silicide layer can be formed on both the gate conductive layer and the elevated SiGe layer after the capping layer is selectively removed.
Since an elevated SiGe layer is formed on the source/drain with a shallow junction in this invention, the resistance of the source/drain can be lowered effectively. Therefore, the source/drain can be formed with a shallower junction to prevent the short channel effect and junction leakage.
Moreover, by using the method for fabricating a raised source/drain of a semiconductor device of this invention, the reliability of junction contact of the source/drain and even the reliability of the whole device can be improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5281552 (1994-01-01), King et al.
patent: 5403434 (1995-04-01), Moslehi
patent: 6406973 (2002-06-01), Lee
patent: 6426265 (2002-07-01), Chu et al.
patent: 6492216 (2002-12-01), Yeo et al.
Jiang Chyun IP Office
Lindsay, Jr. Walter L
Macronix International Co. Ltd.
Niebling John F.
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