Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2001-12-06
2004-05-18
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
C438S694000, C438S700000, C438S704000, C438S719000, C438S723000
Reexamination Certificate
active
06737355
ABSTRACT:
FIELD OF THE INVENTION
In general, the present invention relates to a method creating thick thermal oxide layers on silicon. Also, the present invention relates to a method of separating high voltage areas within a silicon chip, wafer, or stack of silicon chips, or stack of silicon wafers. The present invention also relates to a method of integrating and connecting vertical feedthroughs in a stack of silicon layers.
BRIEF DESCRIPTION OF THE BACKGROUND ART
Various processes have been developed to create isolation regions in silicon. One of the popular methods of creating isolation regions within a silicon substrate is through thermal oxidation of areas of silicon itself. For example, in U.S. Pat. No. 5,410,176 to Liou et al., issued Apr. 25, 1995, the inventors describe a method for forming isolation structures in an integrated circuit. First step is masking all the active regions on the silicon. After masking recesses are etched into the exposed silicon to a depth on the order of the final thickness of the insulating isolation structure. Sidewall spacers of silicon dioxide, or another insulating amorphous material are disposed along the side walls of the recess, with silicon at the bottom of the recesses exposed. Selective epitaxial growth of silicon is then used to form a layer of silicon within the recesses, preferably to a thickness on the order of half of the depth of the recess. The epitaxial silicon is thermally oxidized, filling the recesses with thermal silicon dioxide, having a top surface which is substantially coplanar with the active regions of the surface.
In U.S. Pat. No. 5,863,826 to Wu et al., issued Jan. 26, 1999, the inventors disclose a method for forming field isolation regions in multilayer semiconductor devices comprising the steps of masking active regions of the substrate, forming porous silicon in the exposed field isolation regions, removing the mask, and oxidizing the substrate. A light ion impurity implant is used to create pores in the substrate. Substrate oxidation proceeds by rapid thermal annealing because the increased surface area of the pores and the high reactivity of unsaturated bonds on these surfaces provides for enhanced oxidation.
In U.S. Pat. No. 5,189,501 to Kawamura et al., issued Feb. 23, 1993, the inventors describe an isolator for isolating semiconductor devices, components of an integrated circuit, on a semiconductor substrate, wherein the isolator is delimited by walls of a trench formed on a top surface of the semiconductor substrate, where the trench filled with a silicon oxide layer deposited by a chemical vapor deposition method. A small ditch created in the middle of a top surface of the silicon oxide layer in the trench is filled with silicon, and at least a top surface of the silicon is thermally oxidized to form another silicon oxide layer.
In U.S. Pat. No. 5,386,142 to Kurtz et al., issued Jan. 31, 1995, the inventors describe a semiconductor structure having environmentally isolated circuit elements disposed thereon. The semiconductor structure has a first semiconductor wafer having a semiconductor element such as a piezoresistive element or any integrated circuit located on a top surface thereof. The first wafer is bonded to a second semiconductor wafer so that the semiconductor element on the first wafer is received in a cavity sealed from the outside environment. The bottom surface of the second wafer is prepared by etching it about a mask pattern so that the pattern projects from the bottom surface, thereby forming a cavity and defining projecting surfaces which are bonded to corresponding projecting areas on the first wafer to create a hermetic seal there between. The second wafer is electrochemically etched to produce porous silicon with regions of non-porous monocrystalline silicon extending between the top and bottom surfaces. The porous areas are thermally oxidized to convert them to silicon dioxide while the nonporous regions bonded to bond pads of the resistive pattern on the first wafer act as extended contacts.
Applicants' review of the background art in general has indicated that in order to handle high voltages the silicon oxide layer needs to be thick. Two micron of silicon oxide layer thickness is needed to handle a voltage of about 1 kV. In order to handle a voltage of 3-5 kV, the silicon oxide layer thickness should be in the range of 6-10 &mgr;m. Generally a thickness of 3 &mgr;m silicon oxide layers can be formed by long wet thermal oxidation. However 3 &mgr;m thickness is not sufficient to handle a voltage of 3-5 kV reliably since pinholes and other artefacts in the oxide can lower the breakdown voltage.
In the field of semiconductor device fabrication, particularly with the continuing trend toward smaller device feature sizes, micromachining technology compatible with semiconductor processing is a necessity. Microcolumns which are miniaturized electron optic devices facilitate smaller device fabrication. Generally, microcolumns are made of pyrex and silicon. But, pyrex can not be machined with as high a precision as silicon. Therefore, it would be advantageous to find a method enabling fabrication of microcolumns out of silicon alone. However to handle high voltages, portions of the silicon need to be converted to silicon oxide which has a thickness in the range of 6-10 &mgr;m. As stated above, with the general methods available today a silicon oxide thickness which can be generated within a reasonable time by wet thermal oxidation is about 3 &mgr;m (which is generated in about approximately 18 hours at a temperature of 1100° C.).
Often, isolation regions are created within silicon structures for various purposes, for example, to often protect circuit elements within one region from interfering with the functions of circuit elements in another region. Some of these isolation regions need to provide insulation from high voltages. In order to accomplish high voltage insulation, it would be useful to be able to partition silicon structures with thick silicon oxide layers having a thickness in the range of about 2 &mgr;m/kV of applied voltage.
Therefore, there is a need to create thick silicon oxide layers within as on the surfaces of silicon structures. For many semiconductor devices, thickness ranging from greater than 3 up to about 10 &mgr;m are particularly useful.
SUMMARY OF THE INVENTION
One of the embodiments of the invention involves a method of forming a thick silicon oxide layer upon or internal to a silicon structure. This embodiment includes a step of etching a plurality of trenches in or openings through a silicon structure. For example, the etching may be conducted by deep dry silicon etching. With respect to the of the plurality of trenches each trench is separated from an adjacent trench by a trench wall. The silicon is then oxidized. During oxidation the silicon expands. Normally, 1 micrometer of silicon is converted to about 2 &mgr;m of silicon oxide. In other words, during the oxidation process a lateral expansion takes place. The invention takes advantage of this phenomenon. By appropriately selecting the thickness of the walls between trenches and the trench opening width, each trench can be entirely filled with silicon oxide by oxidizing the trench walls. The number of trenches required to oxidize a large area is based on time considerations since the oxidation process is a diffusion limited process. The depth of an oxide layer on a silicon structure surface can be determined by fixing the depth of the trenches (the height of the trench walls). The trench walls will be consumed to form a layer of silicon oxide at the surface of the silicon. Deeper trenches can be etched by increasing the aspect ratio during the etch process.
Another embodiment of the invention, pertains to a method of creating isolation regions within a silicon structure, which isolation regions can withstand high voltages. This embodiment involves etching of a trench or opening of desired shape or shapes into the silicon structure creating an opened shaped portion. If a shape is etched completely through
Applied Materials Inc.
Church Shirley L.
Kunemund Robert
Tran Binh X.
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