Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2001-04-30
2004-05-11
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S151000
Reexamination Certificate
active
06735677
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
REFERENCE TO A MICROFICHE APPENDIX
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a memory access system and method to share memory resources between multiple devices in a microprocessor system. More particularly, the invention relates to a memory access system and method to queue memory requests from independent data access devices (herein “IDADs”) and to execute those queued requests in memory.
2. Background of the Invention
In many microprocessor-based systems, the system memory is a main resource shared by many of the system's devices, including the processor core. For example, a typical system may incorporate multiple processor cores (such as digital signal processors, herein “DSPs”), as well as digital memory access controllers (herein “DMAs”), port interface controllers, etc., all of which may require access to the system memory. Any device requiring access to the system's memory will be referred to collectively herein as an independent data access device, or “IDAD.”
Since the IDADs may be performing operations independently from one another in the system, more than one IDAD may seek access to the memory at the same time. Such conflicting demands for the same memory resource have been handled in various ways. For example, a priority system may be established giving certain system devices priority access to the memory over other devices. For instance, the IDADs may be serviced in a round robin format where each IDAD has priority on a rotating basis; or certain IDADs may be given fixed priority over other IDADs (i.e., a processor core may be given priority over all other IDADs so that the processor core will not be delayed), etc. In these systems, an IDAD may be forced to wait for access to the memory while another IDAD, perhaps with greater priority, is accessing the memory. Causing an IDAD to wait for access to the memory may delay the IDAD from performing other operations thereby reducing the IDAD's performance. For instance, in many systems the IDAD must continue to assert the access request (a read or a write) until it can be completed at the memory. Thus, such an IDAD must wait to assert new access requests until previous ones have finished. As a result, the IDAD may be stalled indefinitely while awaiting access to the shared memory. If the IDAD is performing a function required by the system as a whole, such delays could negatively affect the overall system performance.
Another issue in these systems is that each IDAD interfaces directly with the memory. As a result, each IDAD must implement the exact protocol used by the memory so the interface to the IDAD and the memory will work correctly. Often times, memory has relatively stringent timing requirements, data/address formatting requirements, etc., so this may significantly complicate the design of the IDADs.
Moreover, since each IDAD is designed to interface directly with the shared memory, if the memory is ever changed, each IDAD would have to be redesigned to accommodate the different memory protocol. This makes the system inflexible since any change in memory would potentially require each IDAD to be redesigned to observe the memory's timing requirements, address/data formatting, and other protocol required to access the new memory.
For all of the foregoing reasons, these shared memory systems may often be relatively inefficient, complicated to design, and somewhat inflexible.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a novel method and system for efficiently connecting IDADs to a shared memory to reduce delays, while isolating the IDADs from the memory so each IDAD is not required to implement the exact protocol used by the memory. In particular, a parameterizable queued memory access system is provided wherein a programmable number of access requests can be accepted into a queue structure using a relatively simple interface protocol to the IDADs. The memory access system accepts access requests into the queue from the IDADs and executes them at the shared memory. Since the memory access system handles execution of the requests in memory, the IDAD is free to continue its operations after its memory access request has been queued, thereby enhancing the efficiency of the IDAD. For write requests, once the memory is accessed, the process is complete and the request is done. For read requests, once the memory is accessed, the data read from memory is placed in a read buffer for the IDAD to retrieve at its convenience. The memory access system handles the timing and protocol required for the shared memory; therefore, the design of each IDAD is simplified since it no longer has to observe the strict memory protocol. In addition, a change in memory protocol no longer requires changing the IDADs.
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Choi Woo H.
Conley & Rose, P.C.
Kim Matthew
LSI Logic Corporation
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