Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-30
2004-03-30
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S184000, C438S230000, C438S279000, C438S585000, C438S639000
Reexamination Certificate
active
06713337
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Description of Related Art
A self aligned contact (SAC) method has been employed in the pasts to achieve a higher degree of integration in semiconductor devices.
The SAC method is as follows. First, gate electrodes having side wall spacers and offset nitride films (silicon nitride films used for offset) are formed on a substrate. An interlayer insulation film is then formed so as to cover the side wall spacers, offset nitride films, and gate electrodes. After this, contact holes are formed at self-aligning positions utilizing the etching selectivity of the side wall spacers, the offset nitride films, and the interlayer insulation film.
With the miniaturization in design rules today, the exposure mask alignment margin in photolithography is determined by the alignment or mask precision of the apparatus, among other factors. It is therefore considered difficult to achieve a mask alignment margin of less than about 0.07 to 0.08 &mgr;m. The SAC method, however, is suited to increasing the integration of a semiconductor device in that the mask alignment margin can be larger.
The method disclosed in publication I (Japanese Laid-Open Patent Application H10-4190) is an example of a conventional SAC method.
FIG. 8
serves to illustrate a conventional SAC process. The SAC process in publication I will now be briefly described through reference to FIGS.
8
(A) to
8
(D).
As shown in FIG.
8
(A), first, a gate insulation film
101
and a plurality of gate electrodes
105
having offset nitride films
103
are formed on a substrate
107
. With the technique in publication I, the next step is to form side wall spacers
109
composed of silicon nitride film at the side wall
105
a
portions of the gate electrodes
105
, as shown in FIG.
8
(B). An interlayer insulation film
111
composed of a silicon oxide film, for example, is then formed, as shown in FIG.
8
(C).
After this, as shown in FIG.
8
(D), an etching mask
113
having openings corresponding to contact holes is formed. The interlayer insulation film
111
is then etched via this etching mask
113
. As a result, just the interlayer insulation film
111
is selectively etched with respect to the silicon nitride films (the offset nitride films
103
and the side wall spacers
109
). At this point there remain portions protected by the side wall spacers
109
and the offset nitride films
103
. In this way contact holes
115
are formed at self-aligning positions in the interlayer insulation film
111
.
Unfortunately, with the SAC method of publication I, as shown in FIG.
8
(D), the offset nitride films
103
and side walls
109
are formed from silicon nitride films. Consequently, a hot carrier phenomenon tends to occur when the semiconductor elements in the semiconductor device are driven, as disclosed in publication II (T. Mizuno et al., “Hot-Carrier Injection Suppression Due to the Nitride-Oxide LDD Spacer Structure,” IEEE Transactions on Electron Devices, Vol. 38, No. 3, p. 584, March 1991) or publication III (F. C. Hsu and H. R. Grinolds, “Structure-Enhanced MOSFET Degradation Due to Hot-Electron Injection,” IEEE Electron Device Letters, Vol. EDL-5, No. 3, p. 71, March 1984).
According to publications II or III, the hot carrier phenomenon tends to occur in the vicinity of the interface between the silicon oxide film and silicon nitride film (the portion circled with a broken line in FIG.
8
(D)). The hot carrier phenomenon is particularly prone to occur if the silicon oxide film/silicon nitride film interface is close to the substrate. Therefore, a drawback to the semiconductor device in publication I is its large hot carrier injection.
FIG. 9
serves to illustrate an improved version of prior art. In order to suppress hot carrier injection in the technique of publication I, it is proposed, for example, that a thin oxide film be formed over the entire side wall portion of the gate electrodes
105
prior to the formation of the side wall spacers
109
composed of silicon nitride film. In the example shown in FIG.
9
(A), gate electrode side wall oxide films
117
a
are deposited on the surface of the gate electrodes (polysilicon gate electrodes)
105
and the offset nitride films
103
. In the example shown in FIG.
9
(B), thin silicon oxide films
117
b
are formed on the side walls of the gate electrodes
105
.
At the present time, however, as miniaturization is increasing due to higher integration, the gap between adjacent gate electrodes
105
, for example, is already down to about 0.20 &mgr;m. Furthermore, side wall spacers need to be provided to each gate electrode. The slit gap formed between opposing side wall spacers is therefore only about 0.10 &mgr;m or less, for example. In this case, as shown in
FIG. 9
, it is difficult to form the contact holes
115
in self-aligning fashion, as mentioned above. Specifically, the narrow slit gap w tends to cause a phenomenon whereby etching comes to a halt at the interlayer insulation film
111
in this fine slit portion (generally called etch stop). Thus, with the prior art shown in
FIG. 9
, it is difficult to form the side wall spacers
109
while ensuring a slit gap w that is wide enough to prevent etch stop. Consequently, poor contact tends to occur.
SUMMARY OF THE INVENTION
In view of this, it is an object of the present invention to provide a semiconductor device with an SAC structure, and a semiconductor device manufacturing method that makes use of an SAC method, wherein the structure of the semiconductor device and the semiconductor device manufacturing method allow the hot carrier phenomenon and the occurrence of poor contact to be suppressed.
To achieve the stated object, the semiconductor device of the present invention comprises the following unique structure. Specifically, the semiconductor device of the present invention comprises a substrate, a plurality of gate electrodes having offset nitride films and side wall spacers for forming contact holes in a self-aligning fashion, provided on the substrate via a gate insulation film, an interlayer insulation film that covers the gate electrodes, and contact holes that go through the interlayer insulation film between a plurality of gate electrodes. With the present invention, the side wall spacers are constituted from lower side wall spacers that include a silicon oxide film and are provided on the lower sides of the gate electrode side walls, and upper side wall spacers that include a silicon nitride film and are provided on the upper sides of the gate electrode side walls.
With the structure of this semiconductor device, the side wall spacers are constituted by a laminar structure of lower side wall spacers and upper side wall spacers. The upper side wall spacers and the offset nitride films function as stopper films during the formation of the contact holes. The result is a structure in which the contact holes are formed in self-aligning fashion (SAC structure).
Furthermore, since the lower side wall spacers including the silicon oxide films are provided at the lower portion of the gate electrode side walls where the hot carrier phenomenon tends to occur, the silicon oxide film/silicon nitride film interface can be sufficiently isolated from the substrate surface. Accordingly, it is possible to achieve an element structure that suppresses the hot carrier phenomenon better than the prior art shown in FIG.
8
.
With this structure, there is no need to oxidize the gate electrode side walls or to deposit a silicon oxide film over the entire surface of the gate electrode side walls in order to suppress the hot carrier phenomenon, as was the case with the prior art shown in FIG.
9
. Thus, there is less reduction in the width of the slits formed between mutually opposing portions of the side wall spacers provided to each of the adjacent gate electrodes. Therefore, etch stop is less likely to occur, which means that the incidence of poor contact can be reduced.
REFEREN
Jr. Carl Whitehead
Oki Electric Industry Co. Ltd.
Pham Thanhha
Volentine & Francos, PLLC
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