Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-11-07
2003-12-09
Thompson, Craig (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
Reexamination Certificate
active
06660622
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to processes for formation of vertical interconnects in integrated circuits. In particular, the invention relates to the use of a plasma sputter reactor for both etching and deposition.
BACKGROUND ART
Modem integrated circuits include several levels of metallization formed over the active semiconductor circuitry formed in the substrate, most commonly a silicon wafer. The multiple metallization layers are required to interconnect the millions to tens of millions of discrete semiconductor devices formed in a single integrated circuit. For advanced microprocessors, there may be five or more levels of metallization.
Each metallization layer includes a dielectric layer, for example, of silicon dioxide or possibly a low-k dielectric material deposited over the previous layer, a via (or contact) hole etched through the dielectric layer, and a metallization including a vertical metallic plug filled into the hole and a horizontal interconnect formed on top of the dielectric layer.
The formation of vias has become increasingly crucial with the continuing shrinkage of critical dimensions and the transition to copper rather than aluminum interconnects. Contacts to underlying silicon will for the most part not be explicitly described hereafter but can equally benefit from the various aspects of the invention.
A generic via is illustrated in the cross-sectional view of FIG.
1
. It includes a lower dielectric layer
12
(which in the case of a contact is a silicon-containing layer) having formed therein a conductive feature
14
, such as another metallization or, in the case of a contact, a contact region of a transistor. An upper level dielectric layer
16
overlies the lower dielectric layer
12
and the conductive feature
14
. Advanced plasma etching processes etch a via hole
18
through the upper dielectric layer
16
to the vicinity of the conductive feature
14
. This explanation avoids many details about etch stop layers, horizontal interconnects, and advanced structures, particularly including dual damascene, but the fundamental concepts for the invention remain the same.
Prior to filling metallization into the via hole
18
, the hole is lined with a barrier layer
20
to prevent the diffusion of aluminum or copper into the dielectric
16
, which would short out the dielectric between neighboring via, or the diffusion of oxygen from the dielectric
16
into the metallization, which reduces the conductivity of the plug. Only thereafter is a metallization plug
22
filled into the via hole
18
. In the case of copper metallization, the filling process typically includes a physical vapor deposition or sputtering (PVD) deposition of a copper seed layer followed by an electrochemical plating (ECP) of copper into the hole.
The barrier structure has become increasingly important as the lateral critical dimension has shrunk to 0.25 &mgr;m and below while the vertical dimension has remained virtually static at between 0.7 and 1.5 &mgr;m. As a result, the aspect ratio of the via hole
18
has increased, and the electrical resistance of the vertical electrical metallization has become increasingly important. This emphasis on reduced vertical impedance has been further heightened by the substitution of copper for aluminum as the most desired metallization since copper has a lower bulk resistivity. However, the controlling parameter is the total resistance along a path, including the resistance through the bottom barrier layer portion
24
at the bottom of the via
18
. Particularly in the case of an inter-metal dielectric between two metallizations of the same metal, there is no need to include the bottom barrier layer portion
24
since the copper or other metal in the via
22
will be contacting a same metal in the conductive feature
14
.
In U.S. Pat. No. 5,985,762, Geffken et al. have disclosed directionally etching away the barrier layer exposed on horizontal surfaces of a copper dual-damascene structure but leaving the barrier layer on the sidewalls to protect the dielectric sidewalls from copper sputtered from the underlying copper feature. This process requires presumably a separate etching chamber. Furthermore, the process deleteriously also removes the barrier at the bottom of the trench in a dual-damascene structure. They accordingly deposit another conformal barrier layer, which remains under the metallized via.
In commonly assigned U.S. patent application, Ser. No. 09/518,180 filed Mar. 2, 2000, now issued as U.S. Pat. No. 6,277,249, Gopalraja et al. have suggested that a self-ionized plasma sputter deposition of a copper seed layer for a copper metallization
22
can be used to remove the bottom barrier layer portion
24
.
Accordingly, it is desired to provide a structure and method of making it which reduces the contact resistance at the bottom of a via.
It is further desired to provide such structure and method without unduly complicating the integrated circuit fabrication process.
SUMMARY OF THE INVENTION
One aspect of the invention includes removing a barrier layer formed at the bottom of a via by a sputter etching process performed in a plasma sputter deposition chamber. The same sputter deposition chamber may advantageously be used to then deposit a second barrier layer.
The invention also includes the aspect of removing the barrier layer at the bottom of the via and simultaneously depositing a second barrier layer on vertically extending sidewalls.
Another aspect of the invention includes removing the barrier layer at the bottom of the via while not removing the barrier layer from some other horizontally extending surfaces. The selective removal can be effected by simultaneously sputter depositing a second barrier layer on these other horizontal surfaces. The selective deposition of the second barrier layer can be advantageously followed by the sputter deposition in the same sputter reactor of another layer of the second barrier layer under different conditions such that the additional layer is also deposited on the via bottom.
The combined process may be performed in an inductively coupled plasma sputter reactor in which, during the removal step, the sputtering target is not energized and thus not sputtered, but, during the deposition of the second barrier layer, it is energized to be sputtered. During the removal step, the inductive coil generates a plasma of the sputtering working gas, and the wafer is biased to attract the working gas ions.
The invention includes structures achievable by the invention in which a barrier layer is coated on the sides of the hole but not its bottom. It also includes a dual-damascene structure in which the barrier is coated on the trench floor but not on the via bottom.
REFERENCES:
patent: 5770519 (1998-06-01), Klein et al.
patent: 5846332 (1998-12-01), Zhao et al.
patent: 5933753 (1999-08-01), Simon et al.
patent: 5985762 (1999-11-01), Geffken et al.
patent: 6017144 (2000-01-01), Guo et al.
patent: 6106625 (2000-08-01), Koai et al.
patent: 6265313 (2001-07-01), Huang et al.
patent: 6277249 (2001-08-01), Gopalraja et al.
patent: 6284657 (2001-09-01), Chooi et al.
patent: 6287977 (2001-09-01), Hashim et al.
patent: 6294458 (2001-09-01), Zhang et al.
patent: 6306732 (2001-10-01), Brown
patent: XP-002223600 (2000-05-01), None
patent: 2000-323571 (2000-11-01), None
Yamagihshi et al., “TEM/SEM Investigation and Electrical Evaluation of a Bottomless 1-PVS Ta(N) Barrier in a Dual Mask”,Advanced Metallization Conference 2000, Proceedings of the Conference 2000, Advanced Metallization Conference 2000, Proceedings of the Conference, San Diego, CA, USA, Oct. 2-5, 2000, 279-285 pp .
Cao Wei
Chen Ling
Ganguli Seshadri
Marcadal Christophe
Applied Materials Inc.
Guenzer Charles S.
Thompson Craig
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