Method for fabricating NOR type flash memory device

Details Method for fabricating NOR type flash memory device Method for fabricating NOR type flash memory device

2002-03-15

2003-10-21

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S263000, C438S524000

Reexamination Certificate

active

06635532

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2001-13618, filed on Mar. 16, 2001, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for fabricating a semiconductor memory device and, more particularly, to a method for fabricating a NOR type flash memory device.
2. Description of the Related Art
As is known, much effort is being spent on reducing the sizes of semiconductor memory devices. In case of a NOR type flash memory (referred to a ‘NOR flash memory’ hereinafter), one approach used to reduce the device size is to form buried common source lines made of an impurity diffusion layer, self-aligned with word lines. However, as the semiconductor devices become high integrated, the width of the common source line is inevitably decreased, undesirably resulting in an increase of parasitic resistance in the buried common source line. Furthermore, if a trench isolation technique is used in place of a local oxidation of silicon (LOCOS) to avoid problems such as bird's beak encroachment in field oxide layers, the sidewalls of the isolation trenches have vertical sidewall profiles relative to a surface of the semiconductor substrate. Thus, when the semiconductor substrate is exposed to form the common source line after removing the field oxide layer between source regions of cell transistors, the area of the exposed trench sidewalls is increased. As a result, it is difficult to reduce the resistance of the common source line because impurity diffusion layers formed on the exposed sidewalls in the semiconductor substrate are too shallow as shown in FIG.
2
A.
FIG. 1
is a layout diagram of part of a cell array of a conventional NOR flash memory cell.
FIGS. 2A and 2B
are schematic cross-sectional views showing the conventional NOR flash memory cell structure, taken along the line I-I′, and the line II-II′ of the pattern shown in
FIG. 1
, respectively.
In
FIGS. 2A through 11B
, a reference mark A shows a cross-sectional view of word lines, and B shows a cross-sectional view of a common source line, taken along the line I-I′ shown in
FIG. 1. A
reference mark C shows a cross-sectional view of active regions disposed between the word lines, and D shows a cross-sectional view of the word lines formed on top of a field oxide layer, taken along the line II-II′.
Referring to
FIG. 1
, the conventional NOR flash memory cell structure defines active regions by an isolation layer such as a field oxide layer
105
disposed along one direction on the semiconductor substrate. A plurality of word lines WL overlying floating gate patterns are arranged in parallel with each other in the active region extending across the field oxide layer
105
. Further, drain and source regions are formed along the sides of the respective word lines WL. The source regions form a common source line
113
where the field oxide layers between the source regions of the word lines WL are removed and thus the semiconductor substrate is exposed along the word lines WL. A bit line
118
for connecting a peripheral circuit or external power supply is electrically connected to a drain region
114
through a bit line plug
117
.
Referring to
FIGS. 2A and 2B
, the surface of a common source line
213
a
of the conventional NOR flash memory cell has severely stepped sidewalls
212
. Thus, if the impurity diffusion layer is formed on the exposed sidewalls
212
to form a common source line
213
a
using conventional ion-implantation techniques, it is difficult to reduce the electrical resistance of the common source line due to a shallow depth of the impurity diffusion layer formed on the stepped sidewalls
212
(the common source line
213
a
). As a result, device characteristics of the flash memory cell as well as a uniformity of characteristics in each region of a cell array can be degraded. It may be possible to reduce the resistance of the common source line
213
a
by forming the impurity diffusion layer on the sidewalls
212
of the trench region through an oblique ion-implantation that is recently introduced. However, even with this oblique ion-implantation technique, there is a limit to reduce the resistance of the common source line because the surface of the substrate having exposed sidewalls
212
is quite uneven as illustrated in FIG.
2
A.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating a flash memory device overcoming the problems discussed.
Accordingly, a method for fabricating a NOR type flash memory device includes forming a field oxide layer and concurrently defining a plurality of active regions in a semiconductor substrate. A floating gate pattern is formed in the active regions, and then an inter-gate dielectric film, a control gate film, and a capping insulating film are formed over the resultant structure where the floating gate pattern is formed. The capping insulating film, the control gate film, the inter-gate dielectric film, and the floating gate pattern are sequentially etched, and thus a plurality of word lines are formed across the active regions. A common source line region is formed by etching an exposed semiconductor substrate and the field oxide layer along one sidewall of the respective word lines. In the common source line region and the active region exposed along the other sidewall of the word lines, impurities are implanted by an ion-implantation method, and thus a common source line and a drain region are formed.
The common source line region is self-aligned with the wordline, and is formed by etching the semiconductor substrate exposed along one sidewall of the respective word lines and then etching the field oxide layer.
The foregoing features and advantages of the invention will be more fully described in the accompanying drawings.


REFERENCES:
patent: 5661057 (1997-08-01), Fujiwara
patent: 5736442 (1998-04-01), Mori

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