Power MOS device with buried gate

Details Power MOS device with buried gate Power MOS device with buried gate

2002-07-16

2003-10-28

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S128000, C438S209000, C438S212000, C438S268000

Reexamination Certificate

active

06638826

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to MOS semiconductor devices and, more particularly, to a power MOS semiconductor device with continuous body contact and a wide active channel.
BACKGROUND OF THE INVENTION
Co-pending, commonly assigned U.S. application Ser. No. 09/260,411, filed Mar. 1, 1999 by Christopher B. Kocon et al. for MOS-GATED DEVICE HAVING A BURIED GATE AND PROCESS FOR FORMING SAME, the disclosure of which is incorporated herein by reference, describes a device expected to provide high cell packing density through the use of a recessed and buried gate.
FIG. 1
(
FIG. 2
in application Ser. No. 09/260,411) depicts a trench MOS-gated device
200
that includes a doped N+ substrate
201
on which is deposited an epitaxial doped upper layer
202
. Epitaxial layer
202
includes drain region
203
, heavily doped P+ body regions
204
, and P−well regions
205
. Abutting body regions
204
in epitaxial layer
203
are heavily doped N+ source regions
206
, which are separated from each other by a gate trench
207
that has dielectric sidewalls
208
and floor
209
. Contained within trench
207
is a gate material
210
, filled to a selected level
211
, and an overlying dielectric layer
212
. Selected level
211
of gate material
210
is approximately coplanar with the selected depth
216
of N+ source regions
206
, thereby providing overlap between source regions
206
and gate material
210
. The surface
213
of gate dielectric layer
212
is substantially coplanar with the surface
214
of epitaxial layer
202
. Deposited metal layer
215
contacts body regions
204
and source regions
206
.
FIG. 2
(
FIG. 3B
in application Ser. No. 09/260,411) depicts an alternative prior art trench MOS-gated device
300
that includes a doped N+ substrate
301
, on which is disposed a doped upper layer
302
. Upper layer
302
includes drain region
303
and P−wells
305
. N+ source regions
306
, formed by ion implantation and diffusion to a selected depth
316
in upper layer
302
, are also separated by gate trench
307
. Gate trenches
307
each have dielectric sidewalls
308
and a floor
309
and contain conductive gate material
310
, filled to a selected level
311
, and an overlying dielectric layer
312
. The surface
313
of gate dielectric layer
312
is substantially coplanar with the surface
314
of upper layer
302
. Metal layer
315
is deposited on surface
314
to contact body regions
304
and source regions
306
.
Although the just-described prior art structures are expected to provide high cell packing density, the periodic placement of the P+ body regions produces a high series resistance, resulting in degradation of the electro-thermal dynamic characteristics and ruggedness as well as SOA (Safe Operation Area) of the devices. Also, depending on the total area of the P+ body regions, some loss of channel width can result.
SUMMARY OF THE INVENTION
The present invention is directed to an MOS power device a substrate that comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends from the upper surface of the upper layer through the well region into the drain region. Each trench comprises an insulating material lining its surface, a conductive material filling its lower portion to a selected level substantially below the upper surface of the upper layer, and an insulating material substantially filling the remainder of the trench. A plurality of highly doped source regions of a second conductance type are disposed in the upper layer adjacent the upper portion of each trench, each source region extending from the upper surface to a depth in the upper layer selected to provide overlap between the source regions and the conductive material in the trenches. A “V” groove in each of the highly doped source regions extends through the source regions into the well region and terminates in a nadir. A highly doped body region of a first conductance type is disposed in the well region adjacent both to the nadir of one or more of the grooves and to adjacent source regions penetrated by the grooves. A conductive layer is disposed over the substrate and electrically contacts the body and source regions.
The present invention is further directed to a process for fabricating an MOS power device that comprises: providing a semiconductor substrate comprising an upper layer that has an upper surface and an underlying drain region, and forming a well region of a first conductance type in the upper layer overlying the drain region. A plurality of spaced apart gate trenches, each extending from the upper surface of the upper layer through the well region into the drain region, are formed and lined with an insulating material. A lower portion of each said trench is filled with a conductive material to a selected level substantially below the upper surface of the upper layer, and the upper portion of each trench is substantially filled with an insulating material, thereby forming a plurality of trench gates.
A plurality of highly doped source regions of a second conductance type are formed in the upper layer adjacent the upper portion of each trench, each source region extending from the upper surface to a depth in the upper layer selected to provide overlap between the source regions and the conductive material in the trenches. A “U” groove is formed in each of the highly doped source regions, each groove extending through the source region into the well region and terminating in a nadir. A highly doped body region of a first conductance type is implanted in the well region adjacent the nadir of one or more of the grooves, and also adjacent source regions penetrated by the grooves. A conductive layer is deposited over the substrate for electrically contacting the body and source regions.
The MOS power device of the present invention, which is formed by a completely self-aligned process, avoids the loss of channel width and provides-reduced channel resistance without sacrificing device ruggedness and dynamic characteristics, as well as SOA.


REFERENCES:
patent: 6104061 (2000-08-01), Forbes et al.
patent: 6150693 (2000-11-01), Wollesen
patent: 6236099 (2001-05-01), Boden, Jr.

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