SOI structure and method of producing same

Details SOI structure and method of producing same SOI structure and method of producing same

2002-03-11

2003-12-02

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S149000, C438S295000, C438S296000, C438S297000, C438S405000, C438S406000, C438S407000, C438S408000, C438S409000, C438S410000, C438S411000, C438S412000, C438S413000, C438S766000

Reexamination Certificate

active

06656806

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a Silicon On Insulator structure and method of making the structure that is capable of preventing a short between a Local Inter-Connect and a well when forming the Local Inter-Connect on a Silicon on Insulator structure that has a well-type body contact.
BACKGROUND
Recently, new techniques of forming a single-crystal silicon layer on an insulation layer, a process called Silicon On Insulator (SOI), and of integrating unit-devices on the silicon layer have been developed. In fabricating a semiconductor device by such a technique, a junction capacitance in driving the device can be lowered, thus improving the speed compared to a general bulk device.
In designing the SOI element, in general the silicon substrate and the unit device of an upper layer part are completely separated by a field oxide film within an SOI layer and by a insulation layer, such as a Buried Oxide layer (BOX) separating the silicon upper layer part from the lower silicon substrate. Additionally, there is an active area sealed by the BOX layer and the field oxide film is used as a channel area of a transistor.
However, in designing the SOI element as the above, when a flow of electrons increases by driving a transistor, the electrons collide with silicon within a drain area and generate silicon electrons and holes. As its result, a phenomenon is created where holes are concentrated to a body side, which is represented as the active area surrounded by the field oxide film and the BOX layer, by a potential difference. When the holes are concentrated to the body side, and the device is a bulk device, then the holes are discharged through to ground, thus there is no problem. But in a case of the SOI structure, the BOX layer is buried under the body, thus, the holes can not be discharged to the silicon substrate side and are instead successively accumulated, which causes a floating body effect. The floating body effect changes a voltage in the body and causes a characteristic drop of the device performance, such as a generation of data error since the threshold voltage of a transistor falls, or a dynamic characteristic of an SRAM becomes unstable.
At present, therefore, in order to correct the floating body problem, the SOI is being designed as a well-type body contact structure by using a partial trench isolation (PTI) process. The well type body contact structure is formed in the device design by making a well situated between the BOX layer and the field oxide film, the well being in contact with the active area, so that the holes that are concentrated into the body side on the driving transistor can be discharged through the grounded well.
FIGS. 1
a
and
1
b
show a conventional PTI-SOI structure having the well type body contact structure.
FIG. 1
a
shows a plan layout view of the structure, and
FIG. 1
b
is a cross-sectional view along the A-B-C portion of
FIG. 1
a.
With reference to
FIGS. 1
a
and
1
b
, in the conventional PTI-SOI element, a BOX layer
102
made of insulating material is formed on a silicon substrate
100
, and on the BOX layer, a P-type SOI layer is formed. In a device isolation area within the SOI layer, a well
104
b
, which is grounded, is formed. The well
104
b
has a lower surface in contact with the BOX layer. Further, on the surface of the well
104
b
area, a field oxide film
116
a
is formed, and adjacent to the field oxide film, an active area is formed. A gate line
120
is formed on the field oxide film
116
a
. The gate line connects along the active area of the SOI layer and a given portion of the field oxide film
116
a
. Within the active area of the gate line
120
, along both sides, an N+ type source/drain area
118
of an LDD structure, whose lower surface is in contact with the BOX layer
102
, is formed. Also the structure is designed so that the active area surrounded by the BOX layer
102
, the field oxide film
116
a
and the well
104
b
can be used as a channel area of a transistor and a source/drain.
In this way, by using the PTI process in designing the SOI element, the floating body problem can be solved by discharging the holes that are concentrated to the body side through the grounded well. But, because an Aluminum (Al) wiring line should be formed along the A-B-C line of
FIG. 1
a
by a structural characteristic, an interconnection delay becomes greater than a gate delay of a transistor, namely, a propagation delay time, by increased resistance that comes by reducing chip size. As its result, even though the transistor is made well enough, there is a problem that the element characteristic can not be heightened over some limitation.
In order to solve such a problem, like the bulk device, the wiring line should be replaced from the existing Al to Copper (Cu) as low resistance material. Copper wiring is made by a damascene process, where a deep contact is formed and an intermediate conductive layer like the Local Inter-Connect (LIC) is used in the wiring formation. This is a different process than that used to make Al wiring lines. The fundamental difference between damascene and standard processing is that the metal lines are not etched, but deposited in “grooves” within the dielectric layer, and then excess metal is removed by Chemical-Mechanical Processing (CMP).
By forming the Cu wiring through the introduction of the LIC, a poly gate and the N+ type source/drain area can be directly connected, to effectively perform a layout disposition and also reduce a gate resistance. There is a big improvement in device performance using these methods.
FIGS. 2
a
and
2
b
show a plan layout view and a cross-sectional view, respectively, for a structure having an LIC formed by applying the existing damascene process technique as used to form Cu wiring of the bulk device. In
FIGS. 2
a
and
2
b
, the basic structure is same as the device shown in
FIGS. 1
a
and
1
b
, excepting for an additional specific formation of the LIC
128
through the damascene process. Thus, a separate description for the above structure will be omitted.
However, in forming the LIC of the SOI element by the damascene technique used in the existing bulk process as it is, a problem exists in that the LIC
128
can pierce the field oxide film
116
a
and create a short circuit between the LIC
128
and the well
104
b
, at the reference locations I, as shown in
FIG. 2
b.
This phenomenon occurs because the field oxide film
116
a
is considerably etched together when an insulation layer
122
is etched to form the LIC. Presently, in a case of forming the LIC
128
in a bulk device, it is not a serious problem because the field oxide
116
a
is formed as a thick insulation layer and still insulates the LIC
128
even if partially etched. But, in the case that the field oxide film
116
a
is provided as a PTI structure used to form the SOI element by the body contact structure like
FIG. 2
b
, the surface of the well
104
b
is easily exposed in the etching of the insulation layer
122
, since the field oxide film
116
a
is comparatively thin. As a result, a phenomenon occurs that the LIC
128
becomes short circuited to the well
104
b
in areas under the field oxide film
116
a
, which seriously influences and degrades the operation of circuits including this LIC structure.
The present invention addresses this and other limitations of the prior art.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide an SOI structure and a method of producing the SOI structure, in which a short circuit between an LIC and a well caused by applying the LIC to an SOI element having a well type body contact structure can be prevented. In embodiments of the invention, an LIC forming process is changed so that the LIC on an active area includes a Full Trench LIC (FT-LIC) in manufacturing the SOI element, and the rest of an LIC on a field oxide film or a gate line of an adjacent transistor includes a Partial Trench LIC (PT-LIC). To achieve this structure and these methods, the SOI element includes a BOX layer of insulation materia

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