Void-free interlayer dielectric (ILD0) for 0.18-micron flash...

Details Void-free interlayer dielectric (ILD0) for 0.18-micron flash... Void-free interlayer dielectric (ILD0) for 0.18-micron flash...

2002-09-13

2003-09-30

Nguyen, Vinh P. (Department: 2829)

Active solid-state devices (e.g., transistors, solid-state diode

With specified dopant

C257S270000, C257S272000, C257S288000, C257S408000, C257S403000, C257S430000, C257S635000, C438S197000, C438S231000, C438S232000, C438S249000

Reexamination Certificate

active

06627973

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to flash memory semiconductor devices. More particularly, the present invention relates to 0.18-&mgr;m flash memory semiconductor devices. Even more particularly, the present invention relates to eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices.
BACKGROUND OF THE INVENTION
Currently, the semiconductor industry is experiencing shorting problems associated with the silicon (Si) of a CS59 0.18-mm flash memory technology device coming in contact with a tungsten plug due to void formation within the interlayer dielectric (ILD
0
) boron phosphorous tetraethylorthosilicate (BPTEOS) layer. Void formation has been found to be especially prevalent between drain contacts in related art devices.
FIG. 1
is a scanning electron micrograph (SEM) of such a device, in cross-section, demonstrating such void
10
formation along a “word line” direction between the drain contacts
11
, in accordance with the related art.
FIG. 2
is another SEM illustrating, at higher magnification, a device cross-section in which a barrier metal deposition (BMD)/tungsten material
12
from a plug has extended into the voids
10
formed in the ILD, thereby shorting the neighboring drain contacts
11
, as experienced in the related art devices. Although boron-phosphorous-silica (BP—SiO
2
) films, having a relatively high density, have been deposited using a lower deposition rate, a method for forming BPTEOS films using a lower deposition rate has not been known to the Applicants before their invention. Therefore, a need exists for providing a method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a device thereby formed.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a voidless device thereby formed. More specifically, the present invention provides a method for eliminating voids in the interlayer dielectric material of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer being formed by using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer being formed by using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% boron (B) from triethylborate (TEB: C
6
H
15
O
3
B) and approximately 5% phosphorous (P) from triethylphosphate (TEPO: C
6
H
15
O
4
P).
This two-step deposition process completely eliminates voids in the ILD layer for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low deposition rate such as 8±2 Å/sec is driven by a combination of low flow rates of the precursor materials of B and P dopants and tetraethyl orthosilicate (TEOS; i.e., Si(OC
2
H
5
)
4
). Particularly, a low dopant/TEOS flow (e.g., TEB at 60 g/min±30%, TEPO at 30 g/min±30%, TEOS at 200 g/min±30%) performed at a higher pressure (e.g., 450±250 Torr) during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. The second BPTEOS layer may be deposited at a higher deposition rate such as 100±10 Å/sec. Further, the present invention has the advantage of in-situ deposition of the void-free ILD
0
layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration by preventing crystallization of boron phosphate (BPO
4
) and maintaining the “C
1
” etch process using existing tools such as a heat lamp.


REFERENCES:
patent: 4996167 (1991-02-01), Chen
patent: 5480822 (1996-01-01), Hsue et al.
patent: 5631179 (1997-05-01), Sung et al.
patent: 5972789 (1999-10-01), Jeng et al.
patent: 6469339 (2002-10-01), Onakado et al.
patent: 6524914 (2003-02-01), He et al.

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