Method of forming a semiconductor device having a buffer

Details Method of forming a semiconductor device having a buffer Method of forming a semiconductor device having a buffer

2000-06-13

2003-05-27

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06569740

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to semiconductor devices, and more particularly, to a semiconductor device having a stacked-gate buffer that inhibits parasitic bipolar effects during electrostatic discharge (ESD) or electrical overstress (EOS) and a method of forming such device.
BACKGROUND OF THE INVENTION
As semiconductor devices move to smaller geometries, system level power supply voltages must also be scaled downward. However, system level power supply voltages have scaled at a much slower rate than individual chip supply voltages, requiring high voltage tolerant input and output pads to limit the maximum voltages appearing across semiconductor devices on the integrated circuit that may be damaged by the high voltage. In particular, input and output buffers must utilize certain circuit configurations such as two NMOS (N-channel metal oxide semiconductor) transistors in series (stacked-gate) to protect internal devices from the magnitude of externally applied signals which usually exceed the maximum allowable drain-to-source, drain-to-gate and gate-to-source voltages of the submicron technology used to fabricate the chip. Such buffers must also be capable of withstanding ESD and EOS discharges without being damaged by such events.
A well-known problem that causes buffers to fail during ESD events is a phenomenon known as bipolar snapback. During bipolar snapback, a parasitic bipolar device formed by a n+ diffusion coupled to the bondpad (collector) and a n+ diffusion coupled to the chip V
SS
(emitter), can conduct large amounts of ESD discharge current by means of a self-biased mechanism. The self-biasing results from avalanche-breakdown at the collector/base (i.e. n+ pad to p-substrate) diffusion where avalanche-generated electron-hole pairs are created. The holes generated from this effect migrate towards the emitter where they forward bias the base-emitter junction (i.e. n+ V
SS
to p-substrate) of the parasitic device, thereby turning the device on. Usually, the bipolar device implicitly contained in the NMOS device of the output buffer is the most susceptible. This unavoidable parasitic device is usually the weak link during ESD and EOS events and is almost always the point of failure in the buffer, and consequently, the pad.
One well-known solution to alleviate this parasitic bipolar problem is to add a ballast resistor connected between the drain of the first NMOS transistor and an output pin. This technique helps ensure some added measure of ESD protection in the event of bipolar conduction in the buffer by equally distributing any discharge current through the NMOS transistor (or several fingers forming a single NMOS transistor). The ballast resistor is added to ensure that the failure point at a particular collector-to-emitter voltage V
T2
is greater than the collector-to-emitter voltage, V
T1
, where the current begins to flow in the parasitic bipolar transistor. The relationship between V
T1
and VT
2
is as follows. When several NMOS transistors (or several fingers forming a single NMOS transistor) act as a parasitic bipolar device, such a device relies upon the “snap-back” current-voltage characteristics of the parasitic bipolar transistor formed. As stated above, a current begins to flow through the bipolar transistor at a certain collector-to-emitter voltage, V
T1
, Thereafter the collector-to-emitter voltage decreases as the current increases, “snapping back” from V
T1
. Later, the trend reverses, causing the collector-to-emitter voltage to rise as the current also rises. Eventually, the bipolar transistor fails at another particular collector-to-emitter voltage V
T2
. The ballast resistor ensures that V
T2
is greater than V
T1
so that the first NMOS transistor (or finger of the NMOS transistor) does not breakdown at a voltage less than the voltage at which the second NMOS transistor turns on. This in turn guarantees that the failure current of the complete device is the sum total of its individual components rather than that of the first segment which snaps-back.
However, using the ballast resistor has certain drawbacks. First, the electrical performance of the buffer is deteriorated since the magnitude of the ballast resistance (approximately 50 ohms per finger) is large. Secondly, ballast resistors work best when there is some margin of I
T2
. I
T2
is the destructive failure current threshold associated with V
T2
, the destructive failure voltage. Since ballasting more strongly impacts V
T2
rather than I
T2
, there is only marginal benefit to adding ballast resistance if I
T2
is already low. In most modern submicron semiconductor processes I
T2
is low because of use of shallow salicided source/drain junctions and epitaxial substrates. Thus, the conventional wisdom of adding ballast resistance must be reexamined when designing modern I/O pad circuitry. Thirdly, the ballast resistor adds additional circuitry and further area needed on the substrate which increases costs. The area needed for ballasting is further compounded for the case of the series-connected (stacked-gate) NMOS devices since an enlarged gate-to-gate spacing is needed to reduce bipolar effects in this device. The parasitic bipolar present in the stacked-gate device is formed between the top diffusion connected to the bond pad and the bottom diffusion connected to the chip V
SS
electrode. Thus, increasing the gate-to-gate spacing increases the basewidth of the parasitic device, which reduces bipolar effects. The additional area taken by the ballast resistor only adds to an already enlarged buffer.
A need therefore exists for a stacked-gate buffer that avoids the drawbacks of using a ballast resistor.


REFERENCES:
patent: 4811076 (1989-03-01), Tigelaar et al.
patent: 5019888 (1991-05-01), Scott et al.
patent: 5021853 (1991-06-01), Mistry
patent: 5157573 (1992-10-01), Lee et al.
patent: 5225702 (1993-07-01), Chatterjee
patent: 5440162 (1995-08-01), Worley et al.
patent: 5465189 (1995-11-01), Polgreen et al.
patent: 5578860 (1996-11-01), Costa et al.
patent: 5635746 (1997-06-01), Kimura et al.
patent: 5682054 (1997-10-01), Nakashima
patent: 5747853 (1998-05-01), So et al.
Ajith Amerasekera et al., “Substrate Triggering and Salicide Effects on ESD Performance and Protection Circuit Design in Deep Submicron CMOS Processes,” ©1995 IEEE, pp. 547-550.
Jeremy C. Smith, “A Substrate Triggered Lateral Bipolar Circuit for High Voltage Trolerant ESD Protection Applications,” Advanced Circuit Research Laboratory, Motorola, 4 pages.
S. Ramaswamy et al., “EOS/ESD Analysis of High-Density Logic Chips,” EOS/ESD Symposium, pp. 6.4.1-6.4.6.
Steven H. Voldman et al., “Analysis of Snubber-Clamped Diode-String Mixed Voltage Interface ESD Protection Network for Advanced Microprocessors,”EOS/ESD Symposium 95-43, pp. 1.6.1-1.6.19.

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