Metal patterned structure for SiN surface adhesion enhancement

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S666000, C438S614000, C438S108000, C438S926000

Reexamination Certificate

active

06528417

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication and more specifically to adhesion issues in flip-chip package fabrication.
BACKGROUND OF THE INVENTION
In flip-chip package fabrication, the adhesion strength between the underfill and the passivation layer, generally comprised of silicon nitride (Si
x
N
y
or just SiN), benzocyclobutene (BCB) or polyimide (PI), is one key factor to pass extreme reliability test conditions. Once the underfill material is set and without any surface treatment of the surface of SiN passivation layers, the flip-chip package with cured underfill material is hard pressed to pass extreme reliability tests due to poor adhesion between the underfill and the smooth SiN surface of the passivation layer as nothing exists to anchor the underfill to the SiN passivation layer. Failures occur due to moisture penetration in extreme stress conditions such as in a pressure cooker (PCT) test. Such failures are particularly a problem where an Si
x
N
y
passivation layer is formed over the integrated circuit (IC) surface.
Some attempts have been made to increase the adhesion such as designing different underfill materials or applying surface treatments onto the passivation layer such as physical roughening or, for BCB or PI passivation layers, organic plasma surface treatments.
U.S. Pat. Nos. 5,880,017 and 5,539,153 each to Schwiebert et al. each describe a method of bumping substrates by contained paste deposition.
U.S. Pat. No. 5,656,858 to Kondo et al. describes a semiconductor device having a high adhesiveness to the copper film and the barrier metal at the bump part or LSI wiring part of a flip-chip.
U.S. Pat. No. 5,892,270 to Pan describes an apparatus and method of attaching input/output (I/O) pads of an IC die to package leads.
U.S. Pat. No. 6,153,940 to Zakel et al. describes a solder bump, and a method of making same, of an inhomogeneous material composition for connecting contact pad metallization of different electronic components or substrates in flip-chip technology.
SUMMARY OF THE INVENTION
Accordingly, it is an object of an embodiment of the present invention to provide an improved method of increasing adhesion of underfill materials to a surface.
Another object of an embodiment of the present invention is to provide an method of non-plasma treatment roughening of a surface to increase the roughened surface adhesion to overlying materials.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a composite anchor layer is formed over the upper surface of the structure. The composite anchor layer including at least an upper anchor sub-layer and a lower anchor sub-layer. The upper anchor sub-layer is patterned to form a dense pattern of upper sub-anchors. The lower anchor sub-layer is then patterned using the upper sub-anchors as masks to form lower sub-anchors. The respective upper sub-anchors and lower sub-anchors form a dense pattern of anchors whereby the dense pattern of anchors over the upper surface improve the adhesion of the surface.


REFERENCES:
patent: 151228 (1874-05-01), Kweon et al.
patent: 5441915 (1995-08-01), Lee
patent: 5539153 (1996-07-01), Schwiebert et al.
patent: 5656858 (1997-08-01), Kondo et al.
patent: 5880017 (1999-03-01), Schwiebert et al.
patent: 5892270 (1999-04-01), Pan
patent: 6096649 (2000-08-01), Jang
patent: 6153940 (2000-11-01), Zakel et al.
patent: 6242815 (2001-06-01), Hsu et al.
patent: 0814510 (1997-12-01), None

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