Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-27
2003-01-28
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S424000
Reexamination Certificate
active
06511888
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, using a trench isolation method.
2. Description of the Related Art
Local oxidation of silicon (LOCOS), which is widely used in fabricating semiconductor devices, has an advantage of simplifying the fabrication. For extremely integrated semiconductor devices such as 256M dynamic random access memory (DRAM) devices, a width for device isolation is reduced to be smaller than a predetermined limit so that a problem can occur during a selective oxidation process in the LOCOS. In other words, a punch-through phenomenon occurs, or the thickness of a field oxide film is so reduced that adjacent semiconductor devices cannot be electrically isolated. Recently, a trench isolation method has been proposed for solving the above problems of the LOCOS.
According to one trench isolation method, a pad oxide layer and a pad nitride layer are sequentially deposited on a semiconductor substrate to form a mask pattern. The semiconductor substrate is etched using the mask pattern as an etching mask to form a trench. Subsequently, a thermal oxide film is formed on the inside wall of the trench. Next, a gap filling dielectric layer is deposited on the entire surface of the semiconductor substrate by a chemical vapor deposition method to fill the trench. Next, the gap filling dielectric layer is planarized by a chemical-mechanical polishing method to be substantially level with the pad nitride layer of the mask pattern. Thereafter, the mask pattern is removed, thereby forming a trench isolation layer.
The above trench isolation method solves the problems of the LOCOS method, but the processes are more complicated than those of the LOCOS method, thereby increasing the manufacturing cost. Moreover, since the thick mask pattern has been formed on both sides of the trench when the gap filling dielectric layer is formed to fill the trench, a problem that the substantial aspect ratio of the trench increases occurs due to the thick mask pattern. Consequently, voids may be caused within an isolation layer during the formation of the gap filling dielectric layer.
To prevent an increase in substantial aspect ratio of the trench due to the thick mask pattern, the thickness of the pad nitride layer may be reduced. If the thickness of the pad nitride layer is reduced, however, a problem occurs when the gap filling dielectric layer is planarized by a chemical-mechanical polishing method. In other words, when the pad nitride layer is thin, physical damage such as scratches may occur on the top of the semiconductor substrate due to abrasives contained in slurry used in a chemical-mechanical polishing method. If physical damages such as scratches occurs on the top of the semiconductor substrate, a gate oxide can be deteriorated, thereby decreasing the reliability of a semiconductor device.
SUMMARY OF THE INVENTION
To address the above problems, it is a feature of the present invention to provide a trench isolation method for simplifying fabrication, facilitating filling of a trench, and improving the reliability of a gate insulating layer.
This and other features of the present invention may be achieved by a trench isolation method comprising forming a trench in a semiconductor substrate, forming an isolation layer in the trench, and annealing the semiconductor substrate having the isolation layer in a hydrogen atmosphere.
REFERENCES:
patent: 5258332 (1993-11-01), Horioka et al.
patent: 6037238 (2000-03-01), Chang et al.
patent: 6069091 (2000-05-01), Chang et al.
patent: 6084276 (2000-07-01), Gambino et al.
patent: 6249026 (2001-06-01), Matsumoto et al.
patent: 1999-006961 (1999-01-01), None
Park Jung-woo
Park Kyung-won
Park Tai-su
Song Won-sang
Booth Richard
Lee & Sterba, P.C.
Pompey Ron
Samsung Electronics Co,. Ltd.
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