Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-15
2003-01-28
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S392000, C438S253000, C257S296000, C257S300000
Reexamination Certificate
active
06511873
ABSTRACT:
DESCRIPTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon, i.e., poly-poly, capacitors and metal-insulator-silicon (MIS) capacitors that include Si-containing electrodes and a high-dielectric constant, i.e., high-k, dielectric material having a dielectric constant of greater than about 8.0. The present invention also provides methods for fabricating the inventive FEOL capacitors, which optimize the capacitance per unit area of the device. This optimization, in turn, allows for a significant reduction in semiconductor chip size.
2. Background of the Invention
Dielectric materials in high-density circuits appear as capacitors in dynamic random access memory (DRAM) applications, gate dielectrics in transistors and as decoupling capacitors. The dielectric in these structures is typically silicon dioxide, i.e., SiO
2
, silicon nitride, i.e., Si
3
N
4
, or any combinations thereof. These dielectrics have a relative dielectric constant, i.e., k, of about 8.0 or below.
In the case of capacitors, the main focus is on the development of high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. High capacitance/area devices require the use of dielectric materials that are thin (on the order of about 200 Åor less). The use of conventional, thin low-k dielectrics in today's devices is undesirable since such materials lead to leaky devices. Moreover, as conventional chemical vapor deposited and thermal low-k dielectrics become thinner, it is increasingly becoming more difficult to meet reliability limitations. Therefore, alternatives to conventional, thin low-k dielectrics that do not exhibit the above-mentioned leakage problem are continually being sought in the semiconductor industry.
In the case of FEOL capacitors such as poly-poly capacitors and MIS capacitors, the integration of high-k dielectrics (k of greater than about 8) into the capacitor structure is difficult because of the high-deposition temperatures (typically greater than 600° C.) used in depositing the high-k dielectric onto the silicon-containing electrode. At such high-deposition temperatures, interfacial layers form in the silicon layer which may degrade device performance. In addition, grain boundary leakage paths and lowered barrier heights may result which could lead to devices that are highly unreliable.
In view of the above drawbacks in the prior art, there is a need for fabricating FEOL capacitors that have a high capacitance/area with low series resistance of the top and bottom electrodes. Moreover, there is a need for developing FEOL capacitors that contain a thin high-k dielectric which has improved reliability, leakage currents and stability as compared with prior art FEOL capacitors.
SUMMARY OF THE INVENTION
One object of the present invention is to provide FEOL capacitors such as poly-poly capacitors and MIS capacitors that have a high capacitance/area with low series resistance top and bottom electrodes for high frequency responses.
Another object of the present invention is to provide FEOL capacitors containing a thin high-k dielectric that does not lead to leakage problems and device unreliability.
A further object of the present invention is to provide FEOL capacitors using a method that is easy to implement in existing BiCMOS (bipolar complementary metal oxide semiconductor) processing schemes.
A yet further object of the present invention is to provide FEOL capacitors utilizing methods which allow for significant reduction in chip size, which is especially important in analog and mixed-signal applications where large areas of capacitance are used.
These and other objects and advantages are achieved in the present invention by utilizing the following two methods which both include the formation of a high-k dielectric onto a Si-containing bottom electrode and the formation of a highly doped (on the order of about 1E19 atoms/cm
3
or greater) Si-containing top electrode.
Specifically, in one aspect of the present invention, a MIS capacitor is provided utilizing a BiCMOS or CMOS integration scheme which includes the steps of:
(a) implanting a bottom electrode into a surface of a Si-containing substrate;
(b) forming a high-k dielectric over at least a portion of said bottom electrode, said high-k dielectric having a dielectric constant of greater than about 8.0; and
(c) forming a doped Si-containing electrode over said high-k dielectric, wherein said doped Si-containing electrode comprises an intrinsic base polysilicon layer of a bipolar device.
The above-mentioned method forms a MIS capacitor integrated with a bipolar device which includes an implanted bottom electrode formed in a surface of a Si-containing substrate; a high-k dielectric having a dielectric constant of greater than about 8 formed on a portion of said implanted bottom electrode; and a doped Si-containing electrode formed on said high-k dielectric, wherein said doped Si-containing electrode comprises an intrinsic base polysilicon layer of a bipolar device.
Another aspect of the present invention relates to a method of fabricating a poly-poly capacitor utilizing a BiCMOS processing scheme which includes the steps of:
(a) forming a base polysilicon layer over at least isolation regions;
(b) forming a high-k dielectric over at least a portion of said isolation regions, wherein said high-k dielectric has a dielectric constant of greater than about 8.0; and
(c) forming a doped Si-containing electrode over said high-k dielectric, wherein said doped Si-containing electrode comprises an intrinsic base polysilicon layer of a bipolar device.
The above-mentioned steps result in a poly-poly capacitor that comprises a bottom polysilicon electrode formed over isolation regions that are present in a Si-containing substrate; a high-k dielectric having a dielectric constant of greater than about 8 formed on a portion of said bottom electrode; and a doped Si-containing electrode formed on said high-k dielectric, wherein said doped Si-containing electrode comprises an intrinsic base polysilicon layer of a bipolar device.
In both aspects mentioned above, the top Si-containing electrode, which is also the intrinsic base polysilicon layer of a bipolar device, may be comprised of poly SiGe.
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Ballantine Arne W.
Buchanan Douglas A.
Cartier Eduard A.
Coolbaugh Douglas D.
Gousev Evgeni P.
Cao Phat X.
Sabo, Esq. William D.
Scully Scott Murphy & Presser
Trinh (Vikki) Hoa B.
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