Method for forming a spacer for semiconductor manufacture

Details Method for forming a spacer for semiconductor manufacture Method for forming a spacer for semiconductor manufacture

2001-03-26

2002-10-29

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C430S319000

Reexamination Certificate

active

06472280

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to methods for forming photosensitive material spacers in the manufacture of semiconductor devices.
BACKGROUND OF THE INVENTION
Semiconductor processing often requires spacers for ion implantation. Spacers have been used in process steps, such as transistor lightly-doped drain (LDD) formation and source/drain implantation. LDDs are utilized to reduce hot electron effects in MOS devices. These structures absorb some of the potential in the drain and reduce the resulting electric field. Reducing the electric field also reduces hot electron-induced gate currents, increasing device stability.
In the past, nitride and oxide materials have been utilized for LDD fabrication spacers. Two source/drain implantations are done after formation of a gate. Source/drain regions immediately adjacent to the gate are lightly-doped, and source/drain regions farther from the gate are heavily-doped. Spacers are formed alongside the gate after a light source/drain implantation. Then, a second ion implantation forms heavily-doped regions within the already implanted source/drain regions, farther from the gate. However, spacers can be formed prior to the light source/drain implantation. Then, the source/drain region is heavily-doped with an implantation adjacent to the spacers. Subsequently, the spacers are removed and a lightly-doped implant region is formed adjacent to the gate.
Oxide spacers are often utilized in the formation of self-aligned source/drain regions in metal-oxide-semiconductor (MOS) devices. Self-aligned source/drain silicide (salicide) films are utilized to decrease circuit resistance in devices. As devices shrink, circuit resistance increases. Furthermore, sheet resistivity of shallow-junctions of source/drain regions also increases. Therefore, saliciding processes attempt to overcome this increased resistance. Spacers are formed alongside the gate after source/drain implantation. Then, a refractory metal silicide is formed alongside the spacers. Silicide can be formed in a variety of ways, such as by depositing a layer of refractory metal and annealing, or depositing a refractory metal silicide. Subsequent contacts to the silicided source/drain regions have decreased resistance throughout the contact area.
The common process flow to form a spacer is first to deposit a conformal film, like oxide or nitride, followed by a dry etch. Due to the dry etch process step, the silicon substrate and gate oxide integrity may be degraded. As a result, damaged layers will etch at a faster rate, undesirably altering the thickness of the layers. Another limitation of using oxide or nitride for spacer material is that such layers are often deposited using a high temperature deposition step, which may cause undesirable dopant migration, reflow at undesired times, or other unwanted effects in surrounding device areas. Another problem with using oxide and nitride films for spacer material is that they may not always be removed after the implantation step. Ions implanted into such layers diffuse during subsequent thermal process steps. Thus, if such layers are not of adequate thicknesses, it is hard to control the diffusion of unwanted impurities into device regions masked by the spacers.
There is a need for a spacer material which does not subject surrounding device regions to implantation damage or damage caused by dry etching to form the spacer, as in the case of oxides and nitrides. There is a need for a spacer, which is easy to define on a substrate without the need for precise masking steps. There is a further need for a spacer material that does not require high temperature deposition and is easily removed after its use.
SUMMARY OF THE INVENTION
Spacers are formed in semiconductor devices by controllably exposing and developing a photosensitive material, such that spacers remain, self-aligned with structures formed on substrates. Further processing steps, such as ion implantation, are then performed, with the unexposed photosensitive material masking out the ions. The spacers can then be removed using wet chemical etches. The formation of the spacer does not require high temperatures and, thus, does not damage the substrate. In addition, the spacers are self-aligned with the edges of the structures (topography).
In one embodiment of the invention, a method for forming a lightly-doped drain (LDD) structure on a semiconductor wafer comprises the steps of: defining active areas on the wafer; forming at least one gate on the semiconductor wafer in a defined active area; depositing a photosensitive material onto the wafer; controllably exposing the photosensitive material; developing the photosensitive material to form at least one spacer alongside the gate; implanting a first dose of ions into the active areas; removing the spacers; and implanting a second dose of ions into the active areas.
In another embodiment of the invention, a method for forming a LDD structure on a semiconductor wafer comprises the steps of: defining active areas on the wafer; forming at least one gate on the semiconductor wafer, in a defined active area; implanting a first dose of ions into the active areas, adjacent to the gate; depositing a photosensitive material onto the wafer; controllably exposing the photosensitive material; developing the photosensitive material to form at least one spacer alongside the gate; implanting a second dose of ions into the active area; and removing the spacers.
In another embodiment of the invention, a method for forming a transistor, having salicided source/drain regions on a semiconductor wafer, comprises the steps of: defining active areas; forming at least one gate on the semiconductor wafer in a defined active area; doping source/drain regions; depositing photosensitive polyimde onto the wafer; controllably exposing the polyimide; developing the polyimide to form self-aligned spacers alongside the gate; and forming silicide on the source/drain regions. The spacers are not removed in this embodiment of the invention because polyimde is more stable at high temperatures than other photosensitive material, such as conventional photoresist.
In yet another embodiment of the invention, disposable spacers, formed from unexposed photosensitive material, are utilized to create offsets from protruding structures on a substrate. Use of such disposable spacers permits the formation of complex topographies due to their ease of fabrication and removal.
Spacers, formed from unexposed photosensitive material, are much easier to use than prior art spacers, such as oxide and nitride spacers. Such spacers do not require dry etching for their formation, as do oxide and nitride spacers. Thus, the problem of dry etch-induced lattice damage to surrounding material, such as the gate oxide or silicon substrate, is not present when using spacers described in the invention. Another advantage of using such a spacer is that it does not require a high temperature deposition step and it is easily removed. Due to diffraction and phase shift along the edges of structures during exposure of the photosensitive material, the spacers are formed self-aligned with the structures. No mask or precise alignment of a mask is required, but may be used if desired.


REFERENCES:
patent: 4380866 (1983-04-01), Countryman, Jr. et al.
patent: 4521448 (1985-06-01), Sasaki
patent: 4678542 (1987-07-01), Boer et al.
patent: 4963501 (1990-10-01), Ryan et al.
patent: 4978626 (1990-12-01), Poon et al.
patent: 4994404 (1991-02-01), Sheng et al.
patent: 5096802 (1992-03-01), Hu
patent: 5116460 (1992-05-01), Bukhman
patent: 5132236 (1992-07-01), Doan
patent: 5134058 (1992-07-01), Han
patent: 5243212 (1993-09-01), Williams
patent: 5346586 (1994-09-01), Keller
patent: 5374503 (1994-12-01), Sachdev et al.
patent: 5376483 (1994-12-01), Rolfson
patent: 5393686 (1995-02-01), Yeh et al.
patent: 5395781 (1995-03-01), Wilhoit et al.
patent: 5405791 (1995-04-01), Ahmad et al.
patent: 5472890 (1995-12-01), Oda
patent: 5484744 (1996-01-01), Hong
patent: 5503964 (1996-04-01), Nishina et al.
patent: 5518940 (19

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