Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-29
2002-12-03
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000
Reexamination Certificate
active
06489202
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof and, more particularly, to a structure combining CMOS devices and flash memory cells, which can not only effectively improve the operating efficiency of flash memory cell and CMOS device, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells.
BACKGROUND OF THE INVENTION
Generally, flash memories and CMOS logical circuits are separately designed and fabricated. Although designers can select and match them according to required circuit designs, the volumes after integrated are unsatisfactorily larger for present demands. Nowadays, most products have been standardized, and mutual collocations of most products have specific modes. Therefore, if an IC combining flash memories and CMOS logical circuits is designed according to most of the specifications, the occupied space can be effectively reduced.
Accordingly, the present invention aims to propose a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof, which can not only effectively improve the operating efficiency of flash memory cells and CMOS devices, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells.
SUMMARY OF THE INVENTION
The primary object of the present invention is to provide a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof, wherein flash memory cell structures and CMOS logical devices are simultaneously fabricated on a substrate so that the flash memory cell structures and the CMOS logical devices can be combined and the whole occupied space can be reduced.
The secondary object of the present invention is to provide a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof, wherein CMOS devices capable of performing high-voltage and low-voltage operations are reserved, hence effectively enhancing the whole operating efficiency.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:
REFERENCES:
patent: 5538912 (1996-07-01), Kunori et al.
patent: 6043123 (2000-03-01), Wang et al.
patent: 6187635 (2001-02-01), Kaya
Hsu Ching-Hsiang
Yang Ching-Sung
Booth Richard
e-Memory Technology, Inc.
Hsu Winston
LandOfFree
Structure of an embedded channel write-erase flash memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Structure of an embedded channel write-erase flash memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Structure of an embedded channel write-erase flash memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2991716