Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-14
2002-12-17
Clark, Sheila V. (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S357000, C438S358000, C438S360000, C438S415000, C438S416000, C438S607000, C438S236000, C438S237000, C438S252000
Reexamination Certificate
active
06495421
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method of manufacturing a semiconductor material and to semiconductor devices manufactured using that material. In particular, this invention relates to a method of manufacturing a semiconductor material having an area or zone formed of first regions of one conductivity type interposed with second regions of the opposite conductivity type with the dopant concentration and dimensions of the first and second regions being such that, when the area is depleted in a high voltage mode of operation, the space charge per unit area in the first and second regions balances at least to the extent that the electric field resulting from the space charge is less than the critical field strength at which avalanche breakdown would occur in that area. The area thus provides a voltage-sustaining space charge zone when depleted.
Semiconductor devices having such zones are disclosed in U.S. Pat. No. 4,754,310 (our reference: PHB32740). As set out in U.S. Pat. No. 4,754,310, the provision of such a zone within a semiconductor device enables the individual dopant concentrations and thicknesses of the first and second regions to be controlled so that the effective dopant concentration of the area can be increased independently of the desired breakdown voltage so that the series resistivity of the area is approximately proportional to the breakdown voltage rather than to the square of the breakdown voltage as is the case in conventional devices. The achievement of a lower on-resistance device for a given breakdown voltage is particularly advantageous for high voltage MOSFETs and IGBTs. Other embodiments of semiconductor devices having such zones are disclosed in U.S. Pat. No. 5,438,215 and International Patent Publication No. WO-A-97/29518. The whole contents of U.S. Pat. Nos. 4,574,310 , 5,438,215 and WO-A-97/29518 are hereby incorporated as reference material.
As described in U.S. Pat. Nos. 4,754,310 , 5,438,215 and WO-A-97/29518, epitaxial refill of etched openings may be used to interpose regions of one conductivity type with regions of the opposite conductivity type where the semiconductor device is to be a vertical device, that is where the main current flow path is between first and second major opposed surfaces of the semiconductor device. Neither U.S. Pat. No. 4,754,310 nor U.S. Pat. No. 5,438,215 suggests how such epitaxial refill may be carried out. FIGS. 7A to 7B of WO-A-97-29518 suggest using repeated epitaxy with ion implantation of the opposite type dopant at each epitaxial stage. However, the number of steps involved in this process makes it expensive and, moreover, it is difficult to control the repeated epitaxy and ion implantation processes to achieve the required space charge balancing discussed above.
SUMMARY OF THE INVENTION
It is an aim of the present invention to provide a low-cost, straightforward process for manufacturing a semiconductor material having such an area.
According to one aspect of the present invention, a zone having p-conductivity type and n-conductivity type regions with dopant concentrations and dimensions such that, when the n and p-conductivity type regions are depleted of free charge carriers, the space charge per unit area of the regions balances at least to the extent that the resulting electric field is lower than that at which avalanche breakdown would occur in the area is manufactured by selective epitaxial deposition after which the semiconductor surface is planarised using as an etch stop a mask used to assist selective deposition.
According to another aspect of the present invention, a zone having p-conductivity type and n-conductivity type regions with dopant concentrations and dimensions such that, when the n and p-conductivity type regions are depleted of free charge carriers, the space charge per unit area of the regions balances at least to the extent that the resulting electric field is lower than that at which avalanche breakdown would occur in the area is manufactured by selective epitaxial deposition into at least one opening after which the semiconductor surface is planarised using as an etch stop a mask used to enable definition of the at least one opening.
According to further aspects of the present invention, there are provided a method as set out in claim
1
and a method as set out in claim
9
.
Methods embodying the present invention provide a simple way for forming a voltage sustaining zone. A method embodying the present invention may be used to manufacture a high voltage MOS device, for example a MOSFET or IGBT, in which the zone forms at least part of the drain drift or drain extension region and requires only one more mask stage than is required for the manufacture of high voltage MOS devices which do not have such a zone.
Other advantageous technical features in accordance with the present invention are set out in the appended dependent claims.
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Biren Steven R.
Brock II Paul E
Clark Sheila V.
Koninklijke Philips Electronics , N.V.
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