Method for manufacturing lower electrode of DRAM capacitor

Details Method for manufacturing lower electrode of DRAM capacitor Method for manufacturing lower electrode of DRAM capacitor

1998-12-08

2002-06-11

Zarabian, Amir (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S254000, C438S255000, C438S396000

Reexamination Certificate

active

06403411

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing the lower electrode of a DRAM capacitor.
2. Description of Related Art
As long as the trend for forming highly integrated circuit continues, methods capable of forming devices having smaller dimensions must be developed. Right now, semiconductor devices having sub-micron line width are being manufactured. In the past, the means of increasing the packing density of integrated circuit devices has included the reduction of their structural dimensions. For a DRAM capacitor, that means a reduction of the surface area of its electrode. However, by so doing, the amount of electric charge that can be stored in the capacitor is greatly reduced.
In general, the amount of stored charge within a DRAM capacitor must be above a certain threshold level so that the stored data can be retrieved correctly. When some of the dimensions of a DRAM capacitor are reduced, the maximum amount of charge the capacitor is capable of storing will drop correspondingly. Furthermore, as the charge-storing capacity of the capacitor drops, the frequency of refreshes necessary to compensate for the charges lost due to current leakage must be increased. Constant refreshes will compromise the data processing speed of the DRAM. Hence, a method to reduce the area occupied by a capacitor on a semiconductor substrate without decreasing its storage capacity is a major issue for design engineers.
One solution to the charge storage problem of a DRAM capacitor is to grow hemispherical grain silicon (HSG-Si) over the silicon surface of the lower electrode. Given two capacitors formed using the same materials and having the same distance of separation between upper and lower electrodes, the capacitor with HSG-Si coating on its lower electrode can have twice the capacitance of the one without the coating.
FIGS. 1A through 1C
are cross-sectional views showing the progression of manufacturing steps according to a conventional method of fabricating the lower electrode of a DRAM capacitor. First, as shown in
FIG. 1A
, a source/drain region
120
is formed in a substrate
110
. Then, a dielectric layer
130
is deposited over the substrate
110
. Next, photolithographic and etching operations are carried out to form a node contact opening
140
in the dielectric layer
130
. Thereafter, a low-pressure chemical vapor deposition (LPCVD) method is used to deposit amorphous silicon over the dielectric layer
130
and into the node contact opening
140
to form an amorphous silicon (&agr;-Si) layer
150
a
. Usually, the LPCVD operation is carried out at a temperature of slightly below 520° C. using silane (SiH
4
) as a gaseous reactant.
In general, the process of forming a polysilicon layer and the process of forming an amorphous silicon layer using the LPCVD method are very similar. The main difference lies in their depositing temperatures. Normally, the temperature necessary for forming a polysilicon layer is higher, roughly between 600° C. and 650° C., while the deposition of an amorphous layer requires a lower temperature of between 500° C. and 550° C. This is because a higher processing temperature imparts greater energy to the atoms near the surface of the silicon, and a higher atomic mobility facilitates the nucleation of atoms to form large crystals.
However, lowering the operating temperature will decrease the rate of deposition of amorphous silicon considerably. For example, the rate of deposition is around 100 Å/min at 600° C., but drops to only 25 Å/min at 550° C. If the processing temperature is further reduced to about 520° C., the deposition rate will drop to just 8 Å/min. At present, devices having a line width smaller than 0.25 &mgr;m are often fabricated, requiring the dimensions of a DRAM capacitor to be reduced as well. To maintain sufficient capacitance within a diminished chip area, the capacitor has to extend in the vertical direction, forming a so-called stacked capacitor structure. In other words, the node height of a capacitor NH as shown in
FIG. 1A
has to increase. For example, the node height for a DRAM capacitor in a 0.25 &mgr;m line width integrated circuit must be greater than 6000 Å. Therefore, the time spent depositing an amorphous silicon layer to the necessary thickness is very long. At a depositing rate of about 8 Å/min at 520° C., the time required to deposit an amorphous silicon layer having a thickness of about 8000 Å is roughly 16 hours. Such a long period not only brings down productivity considerably, but also encourages the previously deposited amorphous silicon layer to re-crystallize. The re-crystallized polysilicon lumps
160
are also shown in FIG.
1
A. This re-crystallized polysilicon
160
will affect the subsequent growth of the HSG-Si layer over the silicon layer. To avoid re-crystallization completely, the deposition temperature must drop to below 510° C. However, dropping the deposition temperature will lower the deposition rate even further, causing more efficiency problems.
In addition, to increase the electrical conductivity of the amorphous silicon layer, ions must be doped. There are three conventional methods of doping the amorphous silicon layer. The first method is to implant ions into the amorphous silicon layer directly. The second method is to use a thermal diffusion operation to drive dopants into the amorphous silicon layer. The third method is to carry out ion doping and amorphous silicon deposition in situ. If the third method is used, then diborane (B
2
H
6
) should be chosen as a source of dopants. This is because the higher the diborane concentration, the higher will be the deposition rate of amorphous silicon. On the other hand, if phosphine (PH
3
) or arsine (AsH
3
) is used as the source of dopants, then a higher concentration will decrease the rate of deposition of the amorphous silicon. Diborane can easily disintegrate into unstable BH
3
radicals on the surface of silicon and accelerate the disintegration of silane (SiH
4
), thereby facilitating silicon deposition reaction. Phosphine and arsine, however, tend to be strongly attached to the silicon surface, preventing the disintegration of silane and thereby slowing the deposition rate of silicon.
Next, as shown in
FIG. 1B
, the amorphous silicon layer
150
a
is patterned to form a lower electrode
150
b
. Note that some of the polysilicon lumps
160
embedded within the lower electrode
150
b
are exposed on the surface
165
.
Next, as shown in
FIG. 1C
, a seeding operation is carried out, and then the substrate
110
is annealed in a high vacuum at a temperature between 550° C. to 570° C. Ultimately, HSG-Si 170 is formed over the exposed lower electrode
150
b
, creating a rather large lower electrode
150
c
surface. However, HSG-Si is not grown over the exposed surface
165
, which contains polysilicon
160
. This is because the HSG-Si is formed by using the heat in the annealing operation to re-crystallize the amorphous silicon atoms around the nucleation centers planted during the seeding operation. Since the polysilicon already has a definite degree of crystallinity and its energy state is quite stable, no re-crystallization will happen on the surface of a polysilicon layer, and so HSG-Si cannot grow. Therefore, in the presence of polysilicon
160
, the increase in surface area of the lower electrode
150
c
after growing an HSG-Si layer will be much lower than the potential maximum. Moreover, the annealing temperature (550° C. to 570° C.) is much higher than the deposition temperature (500° C. to 550° C.). Thus, re-crystallization of the amorphous silicon layer to form more polysilicon can occur during the annealing period. Consequently, the area capable of growing HSG-Si is further diminished.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a method that is capable of reducing production time for manufacturing the lower el

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