Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-12-23
2002-11-26
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000
Reexamination Certificate
active
06487688
ABSTRACT:
The present invention generally relates to the testing of digital circuits and, more specifically, to the testing of integrated circuits having tri-state bus drivers and to driver control circuitry for use therewith.
BACKGROUND OF THE INVENTION
Testing of digital systems, such as the core logic of an integrated circuit, is typically performed by loading a test pattern or stimulus into scannable memory elements in the system, operating the system in normal mode for at least one clock cycle of the system clock, capturing the response of the system to the test stimulus, unloading the test response from the system and then comparing the responses obtained in the test to the responses which should have been obtained if the system was operating according to design. Problems arise when the circuit under test includes tri-state bus drivers. Tri-state drivers are used in digital circuits to connect data signals to a common bus under the control of an enable signal. For correct operation of the circuit, there must not be more than one driver enabled active at any given time. This is a requirement that is often not possible to meet in a self-test environment based in scan test methods because random test stimulus values are usually shifted in the scan chains and the circuit combinational logic driving the enable signals does not always guarantee that the enable signals are exclusive.
Various solutions to these problems have been proposed. U.S. Pat. No. 5,528,601 for “Scannable Latch for Multiplexor Control” is concerned with the situation where tri-state bus enable signals are all controlled from scannable elements. While scanning-in test vectors, the invention prevents bus contention by means of a combination of encoders/decoders. However, the proposal does not prevent bus contention during the capture cycle. This is a serious limitation of the proposal. During BIST, this might be fatal.
U.S. Pat. No. 5,513,190 for “Built-in Self-test Tri-state Architecture” is concerned with an arrangement for preventing bus contention. The serial connection of the INHIBIT signals provided limits the frequency of operation during BIST, a significant drawback of the method. Also, the probability of testing the last bus drivers near the end of the serial connection is much less than that of the drivers near the beginning, and thus, potentially leaves some of the faults untested.
U.S. Pat. No. 5,404,359 for “Fail-safe Fault Tolerant Circuit for Manufacturing Test Logic on Application Specific Integrated Circuits” provides a technique for avoiding contention on a bus during normal operation of the circuit due to a malfunction of test circuitry that could become active at an inopportune time. However, the patent does not disclose a method of testing the bus drivers described in the patent.
U.S. Pat. No. 5,136,185 for “Local Tristate Control Circuit” is similar to U.S. Pat. No. 5,513,190, mentioned above and, therefore, suffers from the same drawbacks. The patent provides-a serial connection from one bus driver to the, next indicating whether any of the bus drivers upstream is enabled. The patent differs from the latter in the manner in which the last bus driver is handled. If none of the upstream drivers is enabled, the last driver is forced to be enabled irrespective of the state of the functional enable signal output by the core logic. In this way, a pull-up or bus driver is not necessary to ensure the bus carries a value of 0 or 1. This method has the same disadvantages as the latter and, additionally, the impact of the timing of the enable signal of the last driver is more important than that of method proposed by others. The patent suggests that it is known to use a decoder to ensure that only one driver is enabled at any one time. However, testing the logic generating the bus driver enable signals in functional mode is not tested at all due to limitations of the method. Another disadvantage is that the method results in adding more delay along the path of the functional enable signals.
U.S. Pat. No. 5,285,119 for “Semiconductor Integrated Tri-state Circuitry with Test Means” discloses a method of modifying the tri-state circuit so that it behaves like a combinational network during test mode. This method has the disadvantage that some faults in the bus drivers are not tested and the test must be performed at lower speed.
SUMMARY OF THE INVENTION
The present invention seeks to overcome the difficulties outlined above by a method which involves disabling all drivers during scan intervals and enabling at most a selected one of the drivers during the capture interval by generating a driver select signal for each driver and gating the driver select signal with the circuit functional enable signal for each driver to generate a driver enable signal, the driver select signals being generated in such a manner that at most only the selected one of the drivers is active during the capture sequence. The selected one of the drivers is selected by loading a driver select code into memory elements during the scan-in sequence and decoding the driver select code to produce the driver select signals.
The method of the present invention takes advantage of the fact that a disabling mechanism is usually required for the tri-state drivers while scanning data into the memory elements. The invention provides a decoding circuit, dedicated to test, to implement the method. The decoding circuit operates to enable at most one driver at the end of the test stimulus loading sequence. A driver is only enabled if both its associated enable signal generated by the functional logic and the test-dedicated decoding logic driver select signal are active. The present invention supports various scan methodologies. In a clocked scan methodology, the scan sequence is performed at relatively low speed and the signals of the decoders have plenty of time to propagate to the different tri-state drivers, which may be distributed throughout the chip. The driver control circuit will enable only one driver, even if multiple functional enable signals carry an active value. This way, there is no bus contention and the test can be performed at-speed without adding delay compared to a methodology that uses deterministic patterns generated by an appropriate tool. In the proposed method, the functional circuitry does not need to be modified to implement the decoding in test mode and the insertion of the test circuitry into an integrated circuit can be automated.
One aspect of the present invention is generally defined as an improvement in a method of testing a circuit having two or more tri-state bus drivers, each having a data input, an enable input and a data output, the data outputs being connected together to form a bus, the circuit having core logic, a plurality of scannable memory elements, each having a clock input, an input connected to the output of the core logic and/or an output connected to an input to the core logic, and being configurable in scan mode in which the memory elements are connected to define one or more scan chains and in normal mode in which the memory elements are connected to the core logic in normal operational mode, the core logic generating a data input and a functional enable signal for each the tri-state bus drivers, the bus providing input to the core logic, the method including a shift-in sequence for clocking a test stimulus into the memory elements, a capture operation for capturing the response of the core logic to the test stimulus and a shift-out sequence for clocking captured responses out of the elements for analysis, the method comprising the improvement of:
storing a driver select code signal in scannable memory elements associated with the bus drivers, the driver select code signal identifying at most only one of the driver which is to be active during normal mode;
decoding the output of the associated scannable memory elements and generating a decoded driver select signal for each of the bus drivers;
gating each the decoded driver select signal with a functional driver enable signal for each the driver to ge
Logicvision, Inc.
Sheridan & Ross P.C.
Ton David
LandOfFree
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