Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-27
2002-11-05
Nelms, David (Department: 2816)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S257000, C257S314000, C257S315000
Reexamination Certificate
active
06475847
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to an improved fabrication process for making semiconductor memory devices.
BACKGROUND ART
In general, memory devices such as a Flash electrically erasable programmable read only memory (EEPROM) are known. EEPROMs are a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling.
Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped deeply diffused region and a more heavily doped shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a “stacked gate” structure or word line. The stacked gate structure typically includes: a thin gate dielectric or tunnel oxide layer formed on the surface of substrate overlying the channel region; a polysilicon floating gate overlying the tunnel oxide; an interpoly dielectric overlying the floating gate; and a polysilicon control gate overlying the interpoly dielectric layer. Additional layers, such as a silicide layer (disposed on the control gate), a poly cap layer (disposed on the silicide layer), and a silicon oxynitride layer (disposed on the poly cap layer) may be formed over the control gate. A plurality of Flash EEPROM cells may be formed on a single substrate.
A Flash EEPROM also includes peripheral portions which typically include input/output circuitry for selectively addressing individual memory cells.
The process of forming Flash EEPROM cells is well-known and widely practiced throughout the semiconductor industry. After the formation of the memory cells, electrical connections, commonly known as “contacts”, must be made to connect the stack gated structure, the source region and the drain regions to other part of the chip. The contact process starts with the formation of sidewall spacers around the stacked gate structures of each memory cell. An etch stop or liner layer, typically a nitride material such silicon nitride, is then formed over the entire substrate, including the stacked gate structure, using conventional techniques, such as chemical vapor deposition (CVD). A dielectric layer, generally of oxide such as such as boro-phospho-tetra-ethyl-ortho silicate (BPTEOS) or borophosphosilicate glass (BPSG), is then deposited over the etch stop layer. A layer of photoresist is then placed over the dielectric layer and is photolithographically processed to form the pattern of contact openings. An anisotropic etch is then used to etch out portions of the dielectric layer to form source and drain contact openings in the oxide layer. The contact openings stop at the source and drain regions in the substrate. The photoresist is then stripped, and a conductive material, such as tungsten, is deposited over the dielectric layer and fills the source and drain contact openings to form so-called “self-aligned contacts” (conductive contacts). The substrate is then subjected to a chemical-mechanical polishing (CMP) process which removes the conductive material above the dielectric layer to form the conductive contacts through a contact CMP process.
For miniaturization, it is desirable to dispose adjacent word lines as closely together as possible. A problem associated with the use of a nitride layer as an etch stop layer is that the effective separation between adjacent stacked gate structures is reduced. This is becoming critical as separation between adjacent stacked gate structures diminishes.
Another problem associated with the use of a nitride layer as an etch stop layer is that boron and phosphorus in the dielectric layer may diffuse into the source and drain causing auto-doping problem there. It is known that auto-doping in the source and drain adversely affects device performance.
A solution, which would allow further miniaturization of memory device without adversely affecting device performance or yield while prevent boron and phosphorus in the dielectric from diffusing into the source and drain of the device has long been sought, but has eluded those skilled in the art. As the demand for higher performance devices and miniaturization continues at a rapid pace in the field of semiconductor, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides a method for shrinking a semiconductor device by eliminating an etch stop layer so its stacked gate structures can be positioned closer together.
The present invention provides a method for shrinking a semiconductor device by eliminating an etch stop layer and replacing it with a consumable liner layer so its stacked gate structures can be positioned closer together.
The present invention provides a method for forming a dielectric layer over a liner oxide layer, wherein the liner oxide layer (1) is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and (2) serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer, from auto-doping into the sources and drains.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5814862 (1998-09-01), Sung et al.
patent: 6194784 (2001-02-01), Parat et al.
patent: 6348379 (2002-02-01), Wang et al.
U.S. patent application Ser. No. 09/502,628, Wang et al., filed Feb. 11, 2000.
Chang Chi
Chang Mark S.
Hui Angela T.
Ngo Minh Van
Ramsbey Mark T.
Advanced Micro Devices , Inc.
Ho Tu-Tu
Ishimaru Mikio
Nelms David
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