Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-08
2002-02-19
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S302000, C257S321000, C365S185180
Reexamination Certificate
active
06348378
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor device and to a method of making a non-volatile semiconductor device. The invention provides a reduced program disturbance caused by a punch-through that may occur while programming a selected cell. The invention also ensures an adequate amount of on-cell current thereby facilitating an appropriate and accurate on/off sensing decision.
2. Description of the Related Art
Non-volatile semiconductor devices having a flash memory cell are able to delete and/or store data electronically, and are capable of storing data even without power. These devices therefore are attaining a wide-spread applicability in a variety of technical fields. Among these devices, the NOR-type non-volatile semiconductor device, which is generally related to the present invention, typically is structured to have a plurality of memory cell transistors connected in parallel to a bit line. The NOR-type devices usually have only one transistor connected between a drain and a source, which also are connected to the bit line. This configuration increases the memory cell current and enables a high speed operation.
Because the memory cell is connected to the bit line in parallel, the cells adjacent to a common bit line are over-deleted, or inadvertently deleted, when reading the selected cell. In addition, if the threshold voltage (Vth) of the memory cell transistor becomes lower (for example, 0V) than the voltage applied to the control gate of a non-selected cell, a malfunction (read-disturbance) occurs. The malfunction occurs because current flows regardless of whether the selected cell is in the on or off (on/off) position, and thus, all of the cells are read as on-cells.
In an effort to solve this problem, a memory cell of a non-volatile semiconductor device has been fabricated so that an additional transistor, (for example, a transistor of the selected gate), is further provided between a drain and a source so that the two transistors form one memory cell (i.e., a flash memory cell). Flash memory cells having two transistors in one memory cell, however, are too large, which is in direct contrast to the current trend of minimizing the chip size. Accordingly, these semiconductor devices are not widely utilized.
To solve this problem, the art recently has provided non-volatile semiconductor devices having various structures, including those known as “split gate type semiconductor devices.” In these devices, a word line (i.e., the selected gate and the control gate) typically is formed on an upper part of a floating gate having electrons, and on both sidewalls of the device.
FIG. 1
is a section view illustrating the structure of a flash memory cell of a non-volatile semiconductor device manufactured by SST (Silicon Storage Technology Co. Ltd.).
FIG. 2
is a circuit view illustrating the structure of the entire cell array of this memory cell.
With reference to
FIG. 1
, a conventional flash memory cell of a split gate type semiconductor device can be described structurally as follows. A floating gate
14
, usually made from a polysilicon material, is formed on a predetermined part of a semiconductor substrate
10
having a gate insulating layer
12
disposed thereon. An isolation insulating layer
16
is formed on top of the floating gate
14
, and a tunneling insulating layer
18
that is used for deleting data is formed on the substrate
10
, which includes the isolation insulating layer
16
. The tunneling insulating layer
18
also is formed on both sides of the floating gate
14
.
A word line
20
, usually made from a polysilicide or polycide material, then is formed on a predetermined part of the insulating layers
16
and
18
. The word line
20
serves as a selected gate and a control gate. Channel regions (not shown) under the floating gate
14
and the word line
20
are connected in parallel between the source
22
and the drain
24
. Thus, the memory cell is formed to operate as a selected gate transistor I and a memory gate transistor II. In this configuration, the memory cell transistor is at a high, low or negative Vth state depending upon the amount of electrons present in the floating gate
14
.
Accordingly, the non-volatile semiconductor device having the thus-structured flash memory cell performs a series of operations related to storing, deleting, and reading data as follows. A program related to storing data is performed in a hot electron injection (HEI) or Fowler-Nordheim (F-N) tunnel method. Erasing, which is related to-deleting data, is performed in a F-N method. The following exemplifies a case where the program is performed in a HEI method.
First, a program related to storing data will be described. If a high voltage (for example, {tilde over (=)}12V) is applied to a source
22
of the memory cell at a state where Vss (0V) is applied to a drain
24
through the bit line, the floating gate
14
is arranged to have a predetermined voltage due to a coupling by the voltage. If a predetermined voltage (for example, Vth) is applied to the word line
20
, a channel is formed between the source
22
and the drain
24
, and electrons generated in the drain
24
are injected into the floating gate
14
by the HEI method. As a result, a program is made so that data are written in the erased cell. If the voltage applied to the word line
20
is controlled appropriately, the electric field is magnified around the edge of the floating gate
14
so that the programming effect is increased and the current between the source
22
and drain
24
is decreased, thus reducing the power consumption. If the floating gate
14
is filled with electrons, however, the electrons increase the Vth level in the memory cell. Thus, if the cell is read with a reference voltage (Vref{tilde over (=)}3 to 4V), which can be applied to the control gate of the word line
20
, a channel is not formed because Vth is too high. As a consequence, current cannot flow, and only one state is memorized.
Second, a program related to erasing data and data deletion will be described. If a high voltage (for example, 15V) is applied to the word line
20
of the memory cell at a state when Vss (0V) is applied to the drain
24
and the source
22
through the bit line, electrons stored in the floating gate
14
pass through the tunnel insulating layer
18
in the F-N tunnel method. Electrons flow because of the electric field between the word line
20
and the floating gate
14
, and the electrons flow off to the word line
20
. As a consequence, data deletion is performed.
If the Vth level of the cell is decreased because there are no electrons in the floating gate
14
, and if a reference voltage (Vref{tilde over (=)}3 to 4V) is applied to the control gate of the word line
20
to thereby read the cell, a channel is formed in the cell because of the low Vth. Because the channel is formed, current flows and thus, the device memorizes another state which is different from the first state. Thus, data reading is performed by deciding if there is current in the transistor of the memory cell. The decision is made by applying a predetermined voltage to the bit line and word line
20
of the selected cell.
Table 1 is provided to more fully understand the conditions for the operating voltage typically required for programming, erasing, and reading operations.
TABLE 1
Erase
Program
Read
Word Line
15 V
Vth
Vref
Drain
Vss
Vss
≅2 V
Source
Vss
≅12 V
Vss
If the flash memory cell of the non-volatile semiconductor device is structured as in
FIG. 1
, however, program disturbance can occur when a high voltage is applied during the programming operation. This disturbance can occur because the source (S/Ln) is held in common with the selected cell A
1
, and because 0V is applied to the word line (W/Ln) of the non-selected cell A
2
adjacent to the selected cell A
1
on the same bit line (B/Ln).
In addition, if there is a defect in the tunnel insulating layer
18
, a reverse tunneling disturb is generated causing a
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