Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-04
2002-11-26
Fahmy, Jr., Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S253000, C438S258000, C438S241000, C438S396000, C438S381000, C257S306000, C257S308000, C257S310000
Reexamination Certificate
active
06486021
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to a semiconductor memory device incorporating therein high K dielectric as a capacitor dielectric film.
DESCRIPTION OF THE PRIOR ART
As is well known, a dynamic random access memory (DRAM) with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by downsizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
To meet the demand, there have been proposed several structures for the capacitor, such as a trench type or a stack type capacitor, which are arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.
In attempt to meet the demand, there have been introduced a high K dielectric, e.g., Ta
2
O
5
or the like, as a capacitor thin film in place of conventional silicon oxide film and/or silicon nitride film. Since, however, a Ta
2
O
5
layer is grown with a columnar structure, the grown Ta
2
O
5
layer acts also as a high leakage current path. Therefore, it is very difficult for applying the Ta
2
O
5
layer to a capacitor thin film for use in memory device.
Alternatively, a multi-layer dielectric, e.g., Ta
2
O/TiO
2
or Ta
2
O/Al
2
O
3
, has been proposed to use as a capacitor thin film by using a metal organic chemical deposition (MOCVD) to overcome the above-described problem. However, the MOCVD method makes a foreign material reside in the capacitor thin film. This result enforces the capacitor thin film to be performed a high temperature heat-treatment, which, in turn, generates a defect and a high leakage current in the capacitor thin film.
There are still demands for developing a high K dielectric having a low leakage current which is compatible with a semiconductor process.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor device incorporating therein a high K dielectric as a capacitor dielectric.
It is another object of the present invention to provide a method for manufacturing a semiconductor device incorporating therein a high K dielectric as a capacitor dielectric.
In accordance with one aspect of the present invention, there is provided a semiconductor device for use in a memory cell, comprising: an active matrix provided with a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate and conductive plugs electrically connected to the transistors; a number of lower electrodes formed on top of the conductive plugs; Ta
2
O
5
films formed on the lower electrodes; composite films formed on the Ta
2
O
5
films; and upper electrodes formed on the composite films.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of: a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; b) forming a first conductive layer on top of the active matrix; c) patterning the first conductive layer a predetermined configuration, thereby obtaining a number of lower electrodes; d) forming a Ta
2
O
5
layer on the lower electrodes; e) forming a Ta
2x
Al
2(1−x)
O
y
composite layer on the Ta
2
O
5
layer, x and y representing mole %; f) forming a second conductive layer on the Ta
2x
Al
2(1−x)
O
y
composite layer; and g) patterning the second conductive layer, the Ta
2
O
5
layer and the Ta
2x
Al
2(1−x)
O
y
composite layer into a preset configuration, thereby obtaining the semiconductor device.
REFERENCES:
patent: 5977582 (1999-11-01), Fleming et al.
patent: 6143604 (2000-11-01), Chiang et al.
Kim Min-Soo
Lim Chan
Fahmy Jr. Wael
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hyundai Electronics Industries Co,. Ltd.
Lee Hsien-Ming
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