Method of making vertical field effect transistor having...

Details Method of making vertical field effect transistor having... Method of making vertical field effect transistor having...

2001-03-26

2002-05-14

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000, C438S563000

Reexamination Certificate

active

06387758

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to field effect transistors, and more particularly to a vertical field effect transistor fabricated by growing a semiconductor material within an opening formed through doped insulating materials for defining the drain and source extension junctions of the vertical field effect transistor and through a layer of dummy material deposited between the doped insulating materials for defining the channel region of the vertical field effect transistor.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a common component of a monolithic IC is a planar MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension junction
104
and a source extension junction
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension junction
104
and the source extension junction
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where the MOSFET
100
is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
As the dimensions of the MOSFET
100
are scaled down to tens of nanometers, short-channel effects degrade the performance of the MOSFET
100
. Short-channel effects that result due to the short length of the channel region between the drain extension junction
104
and the source extension junction
106
of the MOSFET
100
are known to one of ordinary skill in the art of integrated circuit fabrication. The electrical characteristics of the MOSFET
100
become difficult to control with bias on the gate electrode
118
with short-channel effects which may severely degrade the performance of the MOSFET.
As the dimensions of the MOSFET
100
are further scaled down to tens of nanometers, short channel effects are more likely to disadvantageously affect the operation of the MOSFET
100
, as known to one of ordinary skill in the art of integrated circuit fabrication. In the conventional planar MOSFET
100
of
FIG. 1
, the gate dielectric
116
and the gate electrode
118
are disposed over one plane of the channel region between the drain and source extension junctions
104
and
106
. However, as the dimensions of the MOSFET
100
are further scaled down to tens of nanometers, control of charge accumulation within the channel region of the MOSFET from a plurality of planes of the channel region is desired to minimize short channel effects.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to fabrication of a vertical field effect transistor having a respective gate dielectric and a respective gate electrode formed at each of a plurality of planes of the channel region of the vertical field effect transistor to minimize undesired short channel effects.
In a general aspect of the present invention, for fabricating a vertical field effect transistor on a semiconductor substrate, a first drain or source contact junction is doped with a first dopant within an active device area of the semiconductor substrate. A bottom layer of doped insulating material is deposited on the semiconductor substrate, and the bottom layer of doped insulating material is doped with a second dopant. A layer of dummy material is deposited on the bottom layer of doped insulating material. A top layer of doped insulating material is deposited on the layer of dummy material, and the top layer of doped insulating material is doped with a third dopant.
An opening is etched through the top layer of doped insulating material, the layer of dummy material, and the bottom layer of doped insulating material. The opening is disposed over the active device area of the semiconductor substrate such that the opening has a bottom wall of the semiconductor substrate. The opening is filled with a semiconductor material to form a semiconductor fill contained within the opening. The semiconductor fill has at least one sidewall with a top portion of the at least one sidewall abutting the top layer of doped insulating material, and with a middle portion of the at least one sidewall abutting the layer of dummy material, and with a bottom portion of the at least one sidewall abutting the bottom layer of doped insulating material.
The layer of dummy material is etched away such that the middle portion of the at least one sidewall of the semiconductor fill is exposed. A gate electrode opening disposed between the top and bottom layers of doped insulating material is formed when the layer of dummy material is etched away. A gate dielectric of the vertical field effect transistor is formed on the exposed middle portion of the at least one sidewall of the semiconductor fill. The middle portion of the semiconductor fill abutting the gate dielectric forms a channel region of the vertical field effect transistor.
The gate electrode opening between the top and bottom layers of doped insulating material is filled with a gate electrode material. The gate electrode material abuts the gate dielectric to form a gate electrode of the vertical field effect transistor. The gate dielectric and the gate electrode formed at the sidewall of the semiconductor fill is disposed on a plurality of planes of the channel region of the vertical field effect transistor. A thermal anneal is performed such that the second dopant diffuses from the bottom layer of doped insulating material into the bottom portion of the semiconductor fill to form a first drain or source extension junction of the vertical field effect transistor, and such that the third dopant diffuses from the top layer of doped insulating material into the top portion of the semiconductor fill to form a second drain or source extension junction of the vertical field effect transistor.
In one embodiment of the present invention, the bottom and top layers of the doped insulating material are comprised of PSG (phospho-silicate glass) such that the second and third dopants are comprised of phosphorous

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