Method of manufacturing a semiconductor memory device

Details Method of manufacturing a semiconductor memory device Method of manufacturing a semiconductor memory device

2001-05-23

2002-01-29

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S238000, C438S761000, C438S626000

Reexamination Certificate

active

06342416

ABSTRACT:

BACKGROUND OF THE INVENTION
The present application claims priority under 35 U.S.C. §119 to Korean Application No. 2000-55208 filed on Sep. 20, 2000, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to a semiconductor memory device and manufacturing method thereof, and more particularly, to a dynamic random access memory device having a capacitor-over-bit line (COB) structure capable of forming a connector for connecting a bit line or a lower electrode of a capacitor with a semiconductor substrate by a one-time mask process, while providing a misalignment margin during the connector formation process, and a manufacturing method thereof.
2. Description of the Related Art
As the integration density of semiconductor devices such as dynamic RAMs (DRAMs) continues to increase, a bit line is formed under a capacitor. In association therewith, a lower electrode connector for connecting a lower electrode of a capacitor with an active area (e.g., a source region of a transistor) of a semiconductor substrate on which a DRAM is formed, and a bit line connector for connecting a bit line and another active area are formed by a two-time mask process, respectively. In this case, the lower electrode connector and the bit line connector, respectively, include a contact plug directly contacting an active area of a semiconductor substrate, and a contact pad disposed between the contact plug and the lower electrode or the bit line.
Since the contact pad and the contact plug forms a contact surface, the overall resistance of the lower electrode connector and the bit line connector increases, which in turn degrades the operating speed of a semiconductor memory device. Furthermore, to form the lower electrode connector and the bit line connector, the step of manufacturing and removing a photo mask is repeatedly performed three or four times, thereby complicating the overall process and increasing the possibility that a semiconductor substrate will suffer damage due to the repeatedly performed mask removing step. Furthermore, as the integration density of a semiconductor memory device continues to increase, there is a limit to securing a misalignment margin when forming contact holes for the contact pad and contact plug described above.
The above problems will now be described with reference to
FIGS. 1-8
. A semiconductor memory device shown in
FIGS. 1
,
2
,
3
,
6
and
8
is divided into a cell area C and a peripheral circuit area P, while only the cell area C of the semiconductor memory device is shown in
FIGS. 4
,
5
and
7
. Hereinafter, a bit line contact plug and a lower electrode contact plug denote a portion directly connected with an active area of a substrate and a gate electrode, respectively, and a bit line contact pad and lower electrode contact pad denote a portion connecting the bit line contact plug with a bit line formed on the substrate and a portion connecting the lower electrode contact plug with a lower electrode, respectively. Either the bit line contact plug (or lower electrode contact plug) or the bit line contact pad (or lower electrode contact pad), or if there are the contact pad and the contact plug, the combination thereof is defined as a bit line contact connector (or lower electrode contact connector).
In
FIG. 1
, an active area of a semiconductor substrate
100
is defined by isolation regions
102
. The isolation regions may be formed by shallow trench isolation (STI) or local oxidation of silicon (LOCOS) technique, and in the case of a highly integrated semiconductor memory device, a STI technique is preferably used. Next, an insulating layer, a polysilicon layer, a metal layer or a metal silicide layer, and a capping layer are formed over the entire surface of the semiconductor substrate
100
on a cell area C and a peripheral circuit area P and patterned to form the gate electrodes G
1
, G
2
, G
3
, G
4
, G
5
, G
6
, G
7
, and G
8
and capping patterns
111
. Each gate electrode G
1
, G
2
, G
3
, G
4
, G
5
, G
6
, G
7
, or G
8
is composed of a gate electrode insulating pattern
104
, a polysilicon pattern
108
, and a metal pattern or a metal silicide pattern
110
. Then, using each gate electrode G
1
, G
2
, G
3
, G
4
, G
5
, G
6
, G
7
, or G
8
as a mask, ions having the opposite conductive type to the semiconductor substrate
100
are implanted into the semiconductor substrate
100
to form drain and source regions
103
and
105
.
The capping layer or the capping pattern
111
may be composed of a material having high selectivity with respect to an interlevel dielectric layer
112
which will later be formed, such as for example a silicon nitride layer, an aluminum oxide layer, or a tantalum oxide layer. Subsequently, an insulating layer is formed over the entire surface of the semiconductor substrate
100
on which the gate electrodes G
1
, G
2
, G
3
, G
4
, G
5
, G
6
, G
7
, or G
8
been formed, and etched back to form a spacer
106
along the sidewall of the gate electrodes G
1
, G
2
, G
3
, G
4
, G
5
, G
6
, G
7
, or G
8
and capping pattern
111
. The spacer
106
may be composed of a material having high selectivity with respect to the interlevel dielectric layer
112
. Here, the structures comprised of the gate electrodes G
1
, G
2
, G
3
, G
4
, G
5
, G
6
, G
7
, or G
8
, the capping pattern
111
and the spacers
106
are referred to as gate electrode structures.
Meanwhile, after having formed the spacer
106
, impurity ions of high concentration are implanted into the semiconductor substrate
100
to form the drain and source regions
103
and
105
having a lightly doped drain and source (LDD) structure, thereby completing first through eighth transistors T
1
, T
2
,T
3
, T
4
, T
5
, T
6
, T
7
, and T
8
. The first through fifth transistors T
1
, T
2
,T
3
, T
4
, and T
5
are formed on the cell area C, while the sixth through the eight transistors T
6
, T
7
, and T
8
are formed on the peripheral circuit area P. Hereinafter, the drain and source regions having a LDD structure are referred to as drain and source regions.
In
FIG. 1
, the transistors T
1
, T
2
, T
3
, and T
4
, or T
6
and T
7
between the isolation regions
102
have channels of the same conductive type. The source region
105
of the second transistor T
2
is in common with that of the first transistor T
1
, and the drain region
103
of the second transistor T
2
is in common with that of the third transistor T
3
. Meanwhile, the fifth transistor T
5
may have the same or opposite conductive type of channel. To have a channel of the opposite conductive type to a substrate, a well (not shown) of the opposite conductive type to the substrate is formed within the substrate to form source and drain regions of an adjacent transistor.
A planarized first interlevel dielectric layer
112
is formed over the entire surface of the semiconductor substrate
100
on the cell area C and the peripheral circuit area P on which the spacer
106
has been formed. Subsequently, the first interlevel dielectric layer
112
on the cell area C is etched to form first contact holes exposing the drain and source regions
103
and
105
of the transistors T
1
, T
2
, T
3
, and T
4
. At this point, if the capping patterns
111
and the spacers
106
are composed of materials having high selectivity to the first interlevel dielectric layer
112
, the first contact holes are formed using a self-aligned etching by the capping patterns
111
and the spacers
106
. Next, a polysilicon layer
114
formed of a conductive material is formed on the first interlevel dielectric layer
112
including the first contact holes.
Referring to
FIG. 2
, chemical mechanical polishing (CMP) or etchback is performed on the polysilicon layer
114
until the top surface of the first interlevel dielectric layer
112
is substantially exposed to form a bit line contact plug
114
b
and lower electrode bit line contact plugs
114
a
and
114
c
connected to the drain region
103
and the source region on the cell area C of the semiconductor subs

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