Method to fabricate a non-smiling effect structure in...

Details Method to fabricate a non-smiling effect structure in... Method to fabricate a non-smiling effect structure in...

1999-04-15

2002-03-19

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S435000, C438S437000, C438S593000

Reexamination Certificate

active

06358796

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the manufacturing of semiconductor memories, and in particular, directed to a split-gate flash memory having a shallow trench isolation with a “non-smiling” structure and to a method of forming the same.
(2) Description of the Related Art
The conventional split-gate flash memory cell of
FIG. 1
a
, as practiced in the present manufacturing line, is found to exhibit relatively small capacitive coupling and low data retention capability. This is because, the relatively thick gate oxide (
20
) separating the floating gate (
30
) from the substrate (
10
) contributes to the reduced coupling between the floating gate (
30
) and the source (
15
) due to the so-called “smiling effect”. Reference numerals (
13
) refer to the drain regions in the cell. Smiling effect occurs at the edge of the floating gate which can be better seen in the enlarged view in
FIG. 1
b
. As is known in the art, floating gate (
30
) is separated from substrate (
10
) by the intervening gate oxide layer (
20
) and from the control gate (
50
) by the intervening intergate oxide (
40
) layer as shown in
FIG. 1
a
. Floating gate, including the overlying polyoxide (
35
) “cap”, and the “smiling” structure are shown in
FIG. 1
b.
“Smiling” effect refers to the thickening of the edges (
25
), or “lips” of the gate oxide underlying the polysilicon floating gate of a memory cell caused—as will be apparent to those skilled in the art—by the diffusion of oxygen (
60
) during the forming of the polyoxide (
35
) over the gate as shown in
FIG. 1
b
. That is, during oxidation, oxygen (
60
) diffuses into the gate (
30
) as well as into gate oxide (
20
) through its edges (
25
) and grows the edges as shown in
FIG. 1
b
. Hence the thickness (b) at edge (
25
) becomes larger than its original thickness (a), thereby resulting in a structure having a “smiling” effect.
The same “smiling” effect is found in the prior art of shallow trench isolation (STI) as shown in
FIG. 1
c
as well. Trench (
90
) depicted in
FIG. 1
c
is lined with an oxide layer (
80
) prior to being filled with isolation oxide (
85
). Because oxygen (
60
) diffuses also readily in oxide, a “smiling” effect develops at edges (
70
) forming large “lips” as shown in
FIG. 1
c
. The thickness and shape of the edge “lips” play an important role in the data retention and the coupling between the gate and the source of a memory cell as will be described more fully below. It is disclosed in this invention a “non-smiling” memory cell structure with a self-aligned STI and a method to form the same. It is further disclosed that the method used provides smaller devices which in turn increase the scale of integration of semiconductor chips.
The importance of data retention capacity and the coupling between the gate and the source of a memory cell has been well recognized since the advent of the one-transistor cell memory cell with one capacitor. Over the years, many variations of this simple cell have been advanced for the purposes of shrinking the size of the cell and, at the same time, improve its performance. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Generally, flash EEPROM cells having both functions of electrical programming and erasing may be classified into two categories, namely, a stack-gate structure and a split-gate structure. A conventional stack-gate type cell is shown in
FIG. 2
a
where, as is well known, tunnel oxide film (
120
), a floating gate (
130
), an interpoly insulating film (
140
) and a control gate (
150
) are sequentially stacked on a silicon substrate (
100
) between a drain region (
113
) and a source region (
115
) separated by channel region (
117
). Substrate (
100
) and channel region (
117
) are of a first conductivity type, and the first (
113
) and second (
115
) doped regions are of a second conductivity type that is opposite the first conductivity type.
One of the problems that is encountered in flash memories is the “over-erasure” of the memory cell contents during erasure operations. As seen in
FIG. 2
a
, the stacked-gate transistor is capable of injecting electrons from drain (
113
), based on a phenomenon known as the Fowler-Nordheim Tunneling Effect, through tunneling oxide layer (
120
) into floating gate (
130
). The threshold voltage of a stacked-gate transistor can be raised by means of such electron injection, and the device is then assumes a first state that reflect the content of the memory cell. On the other hand, during erasure of the memory cell, electrons are expelled from the source (
115
) through tunneling oxide layer (
120
) and out of floating gate (
130
) of the transistor. As a result of this electron removal, the threshold voltage is lowered and thus the device then assumes a second memory state.
During the process of memory content erasure, however, to ensure complete removal of the electrons previously injected, the erasure operation is normally sustained for a slightly prolonged time period. There are occasions when such a prolonged erasure operation results in the removal of excess electrons, i.e., more electrons than were previously injected. This results in the formation of electron holes in the floating gate of the device. In severe cases, the stacked-gate transistor becomes a depletion transistor, which conducts even in the absence of the application of a control voltage at the control gate, (
150
). This phenomenon is known in the art as memory over-erasure.
To overcome the described memory over-erasure problem of stacked-gate type EEPROM devices, a split-gate EEPROM device is used as shown in
FIG. 2
b
. This memory device comprises floating-gate transistor which similarly includes control gate (
150
′), floating gate (
130
′) as in the case of the stacked-gate transistor of
FIG. 2
a
. However, floating gate (
130
′) here covers only a portion of the channel region, (
117
′), and the rest of the channel region, (
119
′), is directly controlled by control gate (
150
′). This split-gate-based memory cell is equivalent to a series connected floating-gate transistor (
117
′) and an enhanced isolation transistor (
119
′), as is schematically represented in
FIG. 2
b
. The principal advantage of such configuration is that isolation transistor (
119
′) is free from influence of the state of floating gate (
117
′) and remains in its off-state, even if floating-gate transistor (
117
′) is subjected to the phenomenon of over-erasure and therefore, is in a conductive state. The memory cell can thus maintain its correct state irrespective of the over-erasure problem.
However, the greatest drawback of such split-gate design is the fact that a reduced number of program/erase cycles are allowed. This reduction is due to the fact that floating gate (
130
′) of this split-gate memory cell configuration is only provided near the drain region (
113
′), which results in different mechanisms occurring for the programming and erasing operations of the device. That is, electron passage must be via a sequence of drain (
113
′) and through tunneling oxide layer (
120
′), and the resulting reduction of allowable program/erase cycles renders the device suitable only for those applications requiring a relatively few number of program/erase cycles during the entire life span of the device.
To program the transistor shown in
FIG. 2
b
, charge is transferred from substrate (
100
) through gate oxide (
120
′) and is stored on floating gate (
130
′) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed “on” of “off.” “Reading” of the cell's st

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