Method of forming high aspect ratio apertures

Details Method of forming high aspect ratio apertures Method of forming high aspect ratio apertures

2000-07-19

2002-01-29

Sergent, Rabon (Department: 1711)

Etching a substrate: processes

Gas phase etching of substrate

Application of energy to the gaseous etchant or to the...

C216S013000, C216S017000, C216S041000, C216S074000, C216S079000, C438S710000, C438S715000, C438S723000

Reexamination Certificate

active

06342165

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming apertures in a dielectric layer overlying a substrate of semiconductor material and, more specifically, to a method of forming high aspect ratio contact apertures through doped silicon dioxide using an inductively coupled etcher.
2. State of the Art
The semiconductor industry's persistence in development efforts to achieve ever-smaller integrated circuitry on the active surfaces of semiconductor substrates consequently necessitates the formation of smaller topographical features defining components of such integrated circuitry. One such feature is the so-called contact aperture, or “contact”, which typically comprises a circular hole extending through a layer of dielectric to a structure formed on or in an underlying semiconductor substrate. As used herein, the term “semiconductor substrate” encompasses not only traditional, substantially circular wafers of silicon and other materials such as gallium arsenide and indium phosphide, but also semiconductor material (usually, but not exclusively silicon) layers carried on supporting substrates, generally categorized as silicon-on-insulator (SOI) structures, including, without limitation, silicon-on-glass (SOG) and silicon-on-sapphire (SOS) structures.
As circuit component structures, including contacts, enter the sub-half micron range of dimensions, tolerances become more critical and demand more precise process parameters. For example, sub-half micron contacts must hold the top contact diameter, or top CD, within a narrow tolerance band while a high aspect ratio contact is etched through a dielectric layer, and the contact itself must exhibit a substantially cylindrical cross section (i.e., little taper) to achieve an effective contact area with the underlying silicon substrate. As used herein, the term “high aspect ratio” as applied to contact structures is currently contemplated to indicate a depth to width, or diameter, ratio of about five to one or more (≧5:1). In addition to contacts, it is also necessary in some instances to etch high aspect ratio sub-half micron width lines or trenches through dielectric layers, and fabrication of these structures demands similar precision.
So-called “dry” or plasma etches have been the process of choice for forming sub-half micron contacts. Current high density (inductively coupled) etch systems, also commonly referenced as “etch tools”, used in manufacturing of integrated circuits are new to the wafer fabrication industry and are still viewed as both difficult and expensive to operate. There is a need in the industry for simpler processes to use in the operation of these etch tools.
For example, it would be highly desirable to etch high aspect ratio contacts through a layer of doped silicon dioxide such as borophosphosilicate glass, or BPSG, and sometimes through additional layers such as other oxides, silicon nitride or inorganic, dielectric anti-reflective coating (DARC) films between the mask and the substrate silicon. Processing requirements for formation of such contact structures dictate the ability to hold top CD for a 2.2 &mgr;m deep feature overetched by 0.4 &mgr;m and to generate a contact profile that is vertical or only slightly tapered. A small (less than 0.025 &mgr;m) increase in the radius of the feature caused by reentrant profile may be tolerated. Desired contact structures to be achieved would have a minimum nominal depth of 2.2 &mgr;m and a top CD of between 0.2 and 0.45 &mgr;m, with in-spec top CD and profile control. High selectivity for BPSG to the substrate silicon is required, as is the ability to etch the other films such as the aforementioned silicon nitride and DARC films.
Applied Materials, Inc. of Santa Clara, Calif. currently offers commercially an inductively-coupled plasma etcher identified as the Dielectric Etch IPS Centura® system (the “IPS system”) for etching high aspect ratio contacts, among other purposes. The IPS system employs an inductively-coupled, parallel plate technology which employs a fluorine scavenger in the form of silicon within the etch chamber in combination with fluorine-substituted hydrocarbon etch gases to achieve an oxide etch having a selectivity to silicon nitride in excess of 10:1. U.S. Pat. No. 5,423,945, assigned to Applied Materials, Inc. discloses the structure and operation of a predecessor apparatus to the IPS system, a schematic of which is shown in FIG.
1
.
IPS system
10
, as depicted in
FIG. 1
, includes an etch chamber
12
primarily defined between a grounded silicon roof
14
, an RF powered (bias) wafer support
16
and a silicon ring
18
surrounding wafer support or chuck
16
, on which wafer
100
is disposed for processing. A plasma
20
, generated over wafer
100
, is confined by a magnetic field as shown in dotted lines at
22
and
24
. Gases are supplied to etch chamber
12
through valved manifold
26
, which is connected to a plurality of gas sources (not shown). Evacuation of etch chamber
12
may be effected, as desired, through valve
28
, as known in the art. RF source power is supplied to inner antenna
30
and outer antenna
32
by RF generator
34
. The antennae
30
and
32
are tuned to resonance for efficient inductive coupling with the plasma
20
. Inner antenna
30
, outer antenna
32
, RF generator
34
and associated circuitry comprise a source network
36
. Bias power is also supplied to wafer support
16
by RF generator
34
. RF generator
34
, supplying power to wafer support
16
, comprises a bias network
38
with associated circuitry as shown. RF bias power is delivered at 1.7±0.2 MHz, RF outer antenna power at 2.0±0.1 MHz, and RF inner antenna power at 2.3±0.1 MHz. Other details of the IPS system
10
being entirely conventional, no further discussion thereof is required.
A plasma etch process initially developed for use with the IPS system employs a gas flow of a relatively high rate and somewhat complex chemistry, relatively high process temperatures and, most notably, CO (carbon monoxide) in the gas mixture. Specifically, the process employs 300-400 (and preferably 358) standard cubic centimeters per minute (sccm) Ar (argon), 55 sccm CO, 82 sccm CHF
3
(trifluoromethane) and 26 sccm CH
2
F
2
(difluoromethane) with a process pressure of 50 mTorr. Source power input is about 1650 watts, apportioned as 1400 watts to the outer antenna and 250 watts to the inner antenna. Bias power is about 800 watts. According to the IPS system manufacturer, the high volume of Ar is purportedly required, or at least desirable, to maintain a plasma state within the etch chamber. CO is included in the gas mixture used with the IPS system to prevent so-called “etch stop”, or the simultaneous and premature cessation of etching during formation of a topographic feature such as a contact. CO is required to suppress etch stop under the relatively high process temperatures employed with the IPS system, notably 145° C. roof
14
and 315° C. ring
16
temperatures. However, it is known that CO use has caused Nickel (Ni) contamination of the etch chamber. The IPS system may be unusually susceptible to such contamination due to the aforementioned presence of a silicon scavenger material within the system chamber. Further, Ni contamination may degrade etch process performance, and it is also well known that Ni contamination of silicon (i.e., of the wafers disposed in the chamber for etching) may degrade transistor performance and reduce yields. Levels of 1e13Ni atoms/cm**2 have been measured on silicon test wafers etched in a Ni-contaminated IPS system chamber. Consequently, the proven risk of Ni contamination from CO gas is high, and so the proposed CO-laden gas mixture would only be acceptable with the IPS system if no alternative existed. Moreover, the process as now designed for use with the IPS system fails to meet the aforementioned top CD and contact profile requirements. Finally, chamber stability under the foregoing proposed process parameters has yet to be established

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