Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-05-27
2008-05-27
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000, C714S030000, C714S724000, C714S727000, C324S073100, C716S030000, C716S030000
Reexamination Certificate
active
07380184
ABSTRACT:
According to an aspect of the present invention, multiple scan enable signals (controlling corresponding scan chains) are used in an integrated circuit, and the scan chains are placed in evaluation mode in non-overlapping durations between scan-in and scan-out operations. In an embodiment, a single clock signal drives the elements in both the scan chains, and the start and end of the non-overlapping durations are timed associated with the edges of the pulses of the clock signal. Multiple pulses of the clock signal may be used between the scan-in and scan-out. According to another aspect of the present invention, the scan elements are conveniently connected to different scan enable signals to take advantage of the non-overlapping durations.
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Brady W. James
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Trimmings John P
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