Method of manufacturing MISFET with low contact resistance

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C257S049000, C257SE21163, C257SE21164, C257SE21165

Reexamination Certificate

active

07977182

ABSTRACT:
Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.

REFERENCES:
patent: 2008/0093676 (2008-04-01), Shingu et al.
patent: 2005-123626 (2005-05-01), None
patent: 2008-60101 (2008-03-01), None
Yoshifumi Nishi, et al., “Interfacial Segregation of Metal at NiSi/Si Junction for Novel Dual Silicide Technology”, Technical Digest, International Electron Device Meeting, 2007, 4 pages.
Yoshifumi Nishi, et al., “Successful Enhancement of Metal Segregation at NiSi/Si Junction Through Pre-Amorphization Technique”, Technical Digest,19.4, Symposium on VLSI Technology, Jun. 15, 2008, 2 pages.
J. Derrien, “Properties of Metal Silicides”, Schottky Barrier Heights of TM Silicides on Si and GaAs, edited by Karen Maex and Marc Van Rossum, Dataviews Series No. 14, INSPEC Publication, 1995, pp. 164-167.

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