Narrow channel width effect modification in a shallow trench...

Semiconductor device manufacturing: process – Chemical etching – Combined with coating step

Reexamination Certificate

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C438S510000, C438S680000, C438S692000, C438S706000, C257SE21170, C257SE21043, C257SE21027, C257SE21058, C257SE21077, C257SE21229, C257SE21304, C257SE21546, C257SE21006, C257SE21267

Reexamination Certificate

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07960286

ABSTRACT:
A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.

REFERENCES:
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patent: 7320919 (2008-01-01), Kim
patent: 7394087 (2008-07-01), Kuh et al.
patent: 7759263 (2010-07-01), Sohn et al.
K. Goto, Y. Tagawa, H. Ohta, H. Morioka, S. Pidin, Y. Momiyama, K. Okabe, H. Kokura, S. Inagaki, Y. Kikuchi, M. Kase, K. Hashimoto, M. Kojima and T. Sugii; High Performance 35 nm Gate CMOSFETs With Vertical Scaling and Total Stress Control for 65 nm Technology, Symposium on VLSI Technology Digest of Technical Papers; 2003; pp. 49-50; Fujitsu Ltd.; Fujitsu VLSI Process Technology Laboratory Ltd.; Tokyo, Japan.
Ming-Han Liao, Tze-Liang Lee, Ling-Yen Yeh and Mong-Song Liang; STI Stress Modulation With Additional Implantation and Natural Pad Sin Mask; U.S. Appl. No. 12/235,329, filed Sep. 22, 2008.
Ming-Han Liao and Tze-Liang Lee; Isolation Region Implant and Structure; U.S. Appl. No. 61/150,220, filed Feb. 5, 2009.

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