Methods of forming insulation layer patterns and methods of...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C257SE21507, C257SE21627, C257SE21658, C438S233000, C438S586000, C438S618000

Reexamination Certificate

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07989335

ABSTRACT:
In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.

REFERENCES:
patent: 10-294367 (1998-11-01), None
patent: 10-2007-0071659 (2007-07-01), None
patent: 10-2008-0060311 (2008-07-01), None

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