Method for forming integrated circuit memory devices with high a

Details Method for forming integrated circuit memory devices with high a Method for forming integrated circuit memory devices with high a

1999-01-19

2000-12-19

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438252, H01L 218242

Patent

active

061626724

ABSTRACT:
An integrated circuit memory device includes a substrate divided into a cell array region, a core region, and a peripheral circuit region. A plurality of memory cells in the memory cell region each comprise a memory cell transistor having first spaced apart source/drain regions of the substrate with a predetermined conductivity. A sensing circuit in the core region of the substrate includes a sensing transistor having second spaced apart source/drain regions of the substrate. Each of the second source/drain regions includes high and low concentration regions of the predetermined conductivity wherein the high and low concentration regions are doped with a common dopant. A peripheral circuit in the peripheral region of the substrate includes a peripheral transistor having third spaced apart source/drain regions wherein each of the third source/drain regions has high and low concentration regions thereof. The high concentration region of the third source/drain regions has a first dopant and the low concentration region of the third source/drain region has a second dopant. Related methods are also discussed.

REFERENCES:
patent: 4878100 (1989-10-01), McDavid
patent: 5021851 (1991-06-01), Haken et al.
patent: 5296399 (1994-03-01), Park
patent: 5324680 (1994-06-01), Lee et al.

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