Semiconductor device having a fin structure and method of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C257SE27027, C257SE21038, C257SE21422, C438S717000, C438S733000, C438S736000

Reexamination Certificate

active

07883972

ABSTRACT:
A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.

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patent: 6642090 (2003-11-01), Fried et al.
patent: 6720619 (2004-04-01), Chen et al.
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patent: 2005/0145932 (2005-07-01), Park et al.
patent: 2005/0250285 (2005-11-01), Yoon et al.
patent: 2006/0113603 (2006-06-01), Currie
patent: 2007/0114612 (2007-05-01), Ahn et al.
patent: 08-139325 (1996-05-01), None
patent: 10-2003-0020644 (2003-03-01), None

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