Methods of forming a field effect transistors, pluralities...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S239000, C257SE21646

Reexamination Certificate

active

07939403

ABSTRACT:
A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially under the channel region along the channel length and with semiconductor material being received over the projections. The trench isolation material is etched to expose opposing sides of the semiconductor material along the channel length. The exposed opposing sides of the semiconductor material are etched along the channel length to form a channel fin projecting upwardly relative to the projections. A gate is formed over a top and opposing sides of the fin along the channel length. Other methods and structures are disclosed.

REFERENCES:
patent: 5466621 (1995-11-01), Hisamoto et al.
patent: 5612230 (1997-03-01), Yuzurihara et al.
patent: 5801083 (1998-09-01), Yu et al.
patent: 6285057 (2001-09-01), Hopper et al.
patent: 6300215 (2001-10-01), Shin
patent: 6642090 (2003-11-01), Fried et al.
patent: 7407847 (2008-08-01), Doyle et al.
patent: 7413955 (2008-08-01), Kim
patent: 2004/0110358 (2004-06-01), Lee
patent: 2004/0110383 (2004-06-01), Tanaka
patent: 2004/0150071 (2004-08-01), Kondo et al.
patent: 2004/0195610 (2004-10-01), Morikado
patent: 2004/0262687 (2004-12-01), Jung et al.
patent: 2005/0136617 (2005-06-01), Jang
patent: 2005/0199932 (2005-09-01), Abbott et al.
patent: 2005/0250279 (2005-11-01), Son et al.
patent: 2006/0046428 (2006-03-01), Baiocco et al.
patent: 2006/0076595 (2006-04-01), Wu
patent: 101 57 785 (2003-06-01), None
patent: 1 229 579 (2002-08-01), None
WO, US2007/022856, Mar. 19, 2008, Written Opinion.
WO, US2007/022856, Mar. 19, 2008, International Search Report.
WO, US2007/022856, May 28, 2009, IPRP.
Yeo, K.H., et al., “80 nm 512M DRAM with Enhanced Data Retention Time Using Partially-Insulated Cell Array Transistor(PiCAT)”, 2004 Symposium on VLSI Technology Digest of Technology, 2004 IEEE, pp. 30-31.
Ananthan, Hari, “FinFET-Current Research Issues”, School of Electrical and Computer Engineering, Purdue University, Lafayette, Indiana 47907.
Kim et al., “S-RCAT (Spereshaped-Recess-Channel-Array Transistor) Technology for 70nm DRAM feature size and beyond”, 2005 Symposium on VLSI Technology Digest, pp. 34-35.
U.S. Appl. No. 11/436,726, filed May 2006, Fischer.
U.S. Appl. No. 11/168,861, filed Jun. 2005, Wang.
US2006/020877, May 2006, PCT Search Report.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods of forming a field effect transistors, pluralities... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of forming a field effect transistors, pluralities..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming a field effect transistors, pluralities... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2620054

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.