Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-10-28
2001-11-20
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S765010
Reexamination Certificate
active
06321352
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers of the type having a separate channel accessing each terminal of an IC being tested, and in particular to a tester that includes a disk drive in each channel as a source of test instructions.
2. Description of Related Art
A typical “per-pin” integrated circuit (IC) tester includes a separate channel for each terminal of an IC to be tested. Each channel includes a vector memory, a sequencer, a formatting circuit and a pin electronics circuit. The IC tester organizes a test into a succession of test cycles. Before the test, a host computer writes a sequence of vectors (data values) into successive addresses of the vector memory. Each vector defines the test activities the formatting and pin electronics circuits are to carry out during a test cycle. Such activities may include setting a test signal input to the DUT terminal to a particular state at a particular time during the test cycle or sampling a DUT output signal appearing at the DUT terminal at a particular time to determine if it is of an expected state. Before each test cycle the sequencer signals the vector memory to read out a vector to tell the formatting and pin electronics circuits what to do during the test cycle.
As ICs and the manner in which they are tested become more complex, the number of cycles per test increases, thereby increasing the size of the vector data sequence that must be stored in the channel's vector memories. Large high-speed vector memories are expensive. Also since it takes more time for a host computer to write a large vector sequence into the vector memory of each channel, the time required to program testers has increased. When a tester has to frequently alternate between two or more different tests, the time required to reprogram the tester limits its throughput.
What is needed is a tester having channels capable of economically storing large amounts of test instructions and which are capable of quickly switching from one type of test to another without requiring extensive reprogramming time.
SUMMARY OF THE INVENTION
An integrated circuit (IC) tester in accordance with the invention includes set of tester channels, each for carrying out a test activity at a separate terminal of an IC device under test (DUT) during each cycle of a test. In accordance with one aspect of the invention, each tester channel includes a disk drive for storing several instruction sets, each including instructions defining a separate test. To configure the tester for performing any one of those tests, a host computer sends a command to each channel identifying the instruction set for that test. Each channel then executes the instructions of the identified set during the test. The host computer may then configure the tester to carry out another one of the tests by commanding the channels to execute another instruction set stored in their disk drives. Since the host computer can configure each channel to perform a test without having to provide the channel with a complete set of instructions from a central source, the tester can quickly switch from one test to another.
In accordance with another aspect of the invention, each channel includes a high-speed instruction memory that can read out instructions at a higher rate than the channel's disk drive. When the host computer commands each channel to execute a set of test instructions stored in its disk drive, the channel moves instructions covering high-speed portions of the test from the disk drive to the instruction memory before the test begins. Thereafter, during portions of the test in which instructions must be read out and executed at a high rate, the channel acquires those instructions from the instruction memory. During portions of the test in which instructions may be executed at a low rate, the channel acquires the instructions to be executed directly from the disk drive. Thus the tester is able to perform tests having a large number of test cycles without having to provide an expensive high-speed instruction memory large enough to hold all needed instructions. The instruction memory need only be large enough to hold the instructions needed for the high-speed portions of the test.
It is accordingly an object of the invention to provide an IC tester having channels capable of economically storing large amounts of test instructions.
It is another object of the invention to provide an IC tester capable of quickly switching from one type of test to another without requiring extensive reprogramming time.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.
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Bedell Daniel J.
Credence Systems Corporation
De'cady Albert
Lamarre Guy
Smith-Hill and Bedell
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