Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-22
2001-11-06
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S213000, C438S225000, C438S262000, C438S263000, C438S279000, C438S524000
Reexamination Certificate
active
06312990
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns a nonvolatle semiconductor memory and, more particularly, the structure of a NOR-type flash electrically erasable and programmable read-only memory (EEPROM).
2. Description of the Related Art
Nonvolable semiconductor memory is typically used in applications for Mask ROM, EPROM, EEPROM, flash EEPROM, etc. Flash EEPROM features immediate electrical erasure of data and low power consumption and, therefore, is typically used as a permanent memory in devices such as a notebook computer or a memory card for a digital camera.
The logical state of the data stored in a nonvolatile semiconductor memory cell is determined by the threshold voltage of the cell transistor. The threshold voltage is defined as the voltage required between the control gate and the source of the cell transistor in order to turn on the transistor. Each cell transistor of an EPROM, EEPROM or flash EEPROM has a floating gate that is isolated from the control gate. The threshold voltage of each cell transistor varies with the amount of charge stored on the floating gate. Thus, data is stored or programmed by increasing or decreasing the amount of charge on the floating gate.
In order to read out data from a programmed cell, the decoder circuit is employed to apply a voltage signal to the cell and the related circuit in order to obtain a current or voltage signal on a bit line for the cell. The current or voltage signal on the bit line represents the data stored in the cell. A sense amplifier connected to the bit line is used to detect the current or voltage signal and identify the data as a logical “1” or “0”.
The structure of the memory cell array is largely classified into NOR-type and NAND-type according to the manner in which the memory cells are connected to the bit lines. A NOR-type structure has each memory cell connected between the bit line and the source line. A NAND-type structure has a string of memory cells connected in series between the bit line and a ground line.
The NOR-type structure is inferior to the NAND-type in view of the scale of integration that can be achieved. However, the NOR-type structure obtains higher operational speed due to higher cell current. Consequently, the NOR-type structure has tended to supplant the NAND-type and the focus of development has been on seeking improvement of the scale of integration of the NOR-type cell transistors.
An example of a NOR-type flash EEPROM is disclosed in an article entitled “A Single Transistor EEPROM Cell and Its Implementation in a 512K CMOS EEPROM” authored by Satyen Mukherjee et al, IEDM, pp. 616-619, 1985. This structure has each bit line commonly connected with two cell transistors. The source region of each of the two cell transistors is extended and connected with a common source line. This requires a bit line contact for the two cell transistors which limit the scale of integration that can be achieved.
In addition, electrical resistance increases with the length of the source region that is extended to the common source line. The increased source resistance of the cell transistors can cause a read or program operation on the cell to fail. Such an operational failure can be prevented by decreasing the interval between the source region and the common source line and by providing a common bit line in place of several bit lines. But the extent of the common source lines makes it difficult to improve the scale of integration of the memory cells.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a cell array structure for a NOR-type flash EEPROM which has a considerably reduced number of bit lines in order to improve the scale of integration and a method for fabricating such a cell array structure.
It is another object of the present invention to provide a cell array structure for a nonvolatile semiconductor memory having reduced source line resistance which allow for large scale integration of the cell array structure and a method for fabricating such a cell array structure.
It is still another object of the present invention to provide a cell array structure for a NOR-type EEPROM which may considerably reduce the extent of the contacts of all bit lines by making a plurality of cell transistors commonly occupy a single bit line and a method for fabricating such a cell array structure.
It is further another object of the present invention to provide the cell array structure for an EEPROM which has a considerably reduced number of bit lines with an increased number of source lines so as to improve the scale of integration and operational reliability and a method for fabricating such a cell array structure.
It is a further object of the present invention to provide a method for fabricating a memory cell array which may prevent a read or program operation from failing.
An embodiment of a nonvolatile semiconductor memory cell array, according to the present invention, is composed of a plurality of unit cell-arrays, wherein each of said unit cell-arrays includes first and second pluralities of cell transistors, where each cell transistor has a control gate, a drain and a source. First and second word lines are included, wherein the first and second word lines are adjacent one another and wherein the first word line is commonly connected to the control gates of the first plurality of cell transistors and the second word line is commonly connected to the control gates of the second plurality of cell transistors. A bit line is commonly connected to the drains of each of the first and second plurality of cell transistors through a bit line contact. First and second source lines are arranged in parallel to one another alongside the bit line. The first source line is connected to a first one of the first plurality of cell transistors through a first source line contact and the first source line is connected to a first one of the second plurality of cell transistors through a second source line contact The second source line is connected to a first one of the second plurality of cell transistors through a third source line contact and the second source line is connected to a second one of the second plurality of cell transistors through a fourth source line contact.
Another embodiment of a unit cell-array, according to the present invention, includes first, second, third and fourth cell transistors each having a control gate, a floating gate, a source and a drain. A first word line is commonly connected with the control gates of the first and second cell transistors. A second word line is commonly connected with the control gates of the third and fourth cell transistors. A bit line is commonly connected with the drains of the first, second, third and fourth cell transistors through a bit line contact A first source line is arranged in parallel with the bit line and commonly connected with the source of the first cell transistor through a first source line contact and with the source of the third cell transistor through a second source line contact. And a second source line is arranged symmetrically with the first source line about the bit line and commonly connected with the source of the second cell transistor through a third source line contact and with the fourth cell transistor through a fourth source line contact.
An embodiment, according to the present invention, of a NOR-type flash memory cell array is composed of a plurality of unit cell-arrays repeatedly arranged, wherein each of said unit cell-arrays includes first, second, third and fourth cell transistors each having a floating gate, control gate, source and drain. A first word line is commonly connected with the control gates of said first and second cell transistors and a second word line is commonly connected with the control gates of said third and fourth cell transistors. A source line is arranged perpendicularly to the word lines and is commonly connected with the sources of the first and second transistors through one source line contact and with the sources of said third
Choi Jeong-hyuk
Kim Keon-soo
Lytle Craig P.
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Smith Matthew
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