Method to form transistors with multiple threshold voltages...

Details Method to form transistors with multiple threshold voltages... Method to form transistors with multiple threshold voltages...

2001-01-25

2001-10-09

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S585000, C438S586000, C438S595000, C438S596000

Reexamination Certificate

active

06300177

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to forming integrated circuit transistors, and more specifically to a method of forming integrated circuit transistor gates that control short channel effects.
BACKGROUND OF THE INVENTION
Deep submicron transistors require special implants, for example pocket implants, to control short channel effects.
U.S. Pat. No. 5,960,270 to Misra et al. describes a gate with SiN spacers
23
and a WF
1
gate, for example metal.
U.S. Pat. No. 5,447,874 to Grivna et al. describes a dual metal gate.
U.S. Pat. No. 5,776,823 to Agnello et al. describes a multi-level (WF) gate.
U.S. Pat. No. 5,966,597 to Wright and U.S. Pat. No. 5,965,911 to Joo et al. describes describe dual material gates.
U.S. Pat. No. 6,051,470 to An et al. describes a dual-gate electrode having edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions and the central conductive portion.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of fabricating a gate with multiple threshold voltages (V
T
).
Another object of the present invention to provide a method of fabricating a gate with multiple threshold voltages by using a combination of different work function gate materials while avoiding special implants.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor substrate having an overlying patterned layer exposing a portion of the substrate within active area and patterned layer opening. The patterned layer having exposed sidewalls. Internal spacers are formed over a portion of the exposed substrate portion within the patterned layer opening on the patterned layer exposed sidewalls. The internal spacers being comprised of a WF
1
material having a first work function. A planarized gate electrode body is formed within the remaining portion of the patterned layer opening and adjacent to the internal spacers. The gate electrode body being comprised of a WF
2
material having a second work function. The internal spacers and the gate electrode body forming the gate electrode.


REFERENCES:
patent: 5356833 (1994-10-01), Maniar et al.
patent: 5447874 (1995-09-01), Grivna et al.
patent: 5686329 (1997-11-01), Chang et al.
patent: 5719068 (1998-02-01), Suzawa et al.
patent: 5776823 (1998-07-01), Agnello et al.
patent: 5912492 (1999-06-01), Chang et al.
patent: 5920076 (1999-07-01), Burgin et al.
patent: 5960270 (1999-09-01), Misra et al.
patent: 5965911 (1999-10-01), Joo et al.
patent: 5966597 (1999-10-01), Wright
patent: 6051470 (2000-04-01), An et al.

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